regop.isa revision 4733
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684519Sgblack@eecs.umich.edu %(op_decl)s; 694519Sgblack@eecs.umich.edu %(op_rd)s; 704688Sgblack@eecs.umich.edu 714688Sgblack@eecs.umich.edu if(%(cond_check)s) 724688Sgblack@eecs.umich.edu { 734688Sgblack@eecs.umich.edu %(code)s; 744688Sgblack@eecs.umich.edu %(flag_code)s; 754688Sgblack@eecs.umich.edu } 764708Sgblack@eecs.umich.edu else 774708Sgblack@eecs.umich.edu { 784708Sgblack@eecs.umich.edu %(else_code)s; 794708Sgblack@eecs.umich.edu } 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 824519Sgblack@eecs.umich.edu if(fault == NoFault) 834519Sgblack@eecs.umich.edu { 844519Sgblack@eecs.umich.edu %(op_wb)s; 854519Sgblack@eecs.umich.edu } 864519Sgblack@eecs.umich.edu return fault; 874519Sgblack@eecs.umich.edu } 884519Sgblack@eecs.umich.edu}}; 894519Sgblack@eecs.umich.edu 904519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 914519Sgblack@eecs.umich.edu Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 924519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 934519Sgblack@eecs.umich.edu { 944519Sgblack@eecs.umich.edu Fault fault = NoFault; 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu %(op_decl)s; 974519Sgblack@eecs.umich.edu %(op_rd)s; 984688Sgblack@eecs.umich.edu 994688Sgblack@eecs.umich.edu if(%(cond_check)s) 1004688Sgblack@eecs.umich.edu { 1014688Sgblack@eecs.umich.edu %(code)s; 1024688Sgblack@eecs.umich.edu %(flag_code)s; 1034688Sgblack@eecs.umich.edu } 1044708Sgblack@eecs.umich.edu else 1054708Sgblack@eecs.umich.edu { 1064708Sgblack@eecs.umich.edu %(else_code)s; 1074708Sgblack@eecs.umich.edu } 1084519Sgblack@eecs.umich.edu 1094519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1104519Sgblack@eecs.umich.edu if(fault == NoFault) 1114519Sgblack@eecs.umich.edu { 1124519Sgblack@eecs.umich.edu %(op_wb)s; 1134519Sgblack@eecs.umich.edu } 1144519Sgblack@eecs.umich.edu return fault; 1154519Sgblack@eecs.umich.edu } 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1194519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1204519Sgblack@eecs.umich.edu { 1214519Sgblack@eecs.umich.edu protected: 1224519Sgblack@eecs.umich.edu void buildMe(); 1234519Sgblack@eecs.umich.edu 1244519Sgblack@eecs.umich.edu public: 1254519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1264519Sgblack@eecs.umich.edu const char * instMnem, 1274519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1284519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1294712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1304519Sgblack@eecs.umich.edu 1314519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1324519Sgblack@eecs.umich.edu const char * instMnem, 1334519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1344712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1354519Sgblack@eecs.umich.edu 1364519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1374519Sgblack@eecs.umich.edu }; 1384519Sgblack@eecs.umich.edu}}; 1394519Sgblack@eecs.umich.edu 1404519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1414519Sgblack@eecs.umich.edu 1424519Sgblack@eecs.umich.edu class %(class_name)sImm : public %(base_class)s 1434519Sgblack@eecs.umich.edu { 1444519Sgblack@eecs.umich.edu protected: 1454519Sgblack@eecs.umich.edu void buildMe(); 1464519Sgblack@eecs.umich.edu 1474519Sgblack@eecs.umich.edu public: 1484519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1494519Sgblack@eecs.umich.edu const char * instMnem, 1504519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1514519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1524712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1534519Sgblack@eecs.umich.edu 1544519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1554519Sgblack@eecs.umich.edu const char * instMnem, 1564519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1574712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1584519Sgblack@eecs.umich.edu 1594519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1604519Sgblack@eecs.umich.edu }; 1614519Sgblack@eecs.umich.edu}}; 1624519Sgblack@eecs.umich.edu 1634519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1644519Sgblack@eecs.umich.edu 1654519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1664519Sgblack@eecs.umich.edu { 1674519Sgblack@eecs.umich.edu %(constructor)s; 1684519Sgblack@eecs.umich.edu } 1694519Sgblack@eecs.umich.edu 1704519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1714519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1724519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1734712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1744519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1754581Sgblack@eecs.umich.edu false, false, false, false, 1764688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1774581Sgblack@eecs.umich.edu %(op_class)s) 1784519Sgblack@eecs.umich.edu { 1794519Sgblack@eecs.umich.edu buildMe(); 1804519Sgblack@eecs.umich.edu } 1814519Sgblack@eecs.umich.edu 1824519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1834519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1844519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1854519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1864712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1874519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1884581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1894688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1904581Sgblack@eecs.umich.edu %(op_class)s) 1914519Sgblack@eecs.umich.edu { 1924519Sgblack@eecs.umich.edu buildMe(); 1934519Sgblack@eecs.umich.edu } 1944519Sgblack@eecs.umich.edu}}; 1954519Sgblack@eecs.umich.edu 1964519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1974519Sgblack@eecs.umich.edu 1984519Sgblack@eecs.umich.edu inline void %(class_name)sImm::buildMe() 1994519Sgblack@eecs.umich.edu { 2004519Sgblack@eecs.umich.edu %(constructor)s; 2014519Sgblack@eecs.umich.edu } 2024519Sgblack@eecs.umich.edu 2034519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 2044519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2054519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2064712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2074519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2084581Sgblack@eecs.umich.edu false, false, false, false, 2094688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2104581Sgblack@eecs.umich.edu %(op_class)s) 2114519Sgblack@eecs.umich.edu { 2124519Sgblack@eecs.umich.edu buildMe(); 2134519Sgblack@eecs.umich.edu } 2144519Sgblack@eecs.umich.edu 2154519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 2164519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2174519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2184519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2194712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2204519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2214581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2224688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2234581Sgblack@eecs.umich.edu %(op_class)s) 2244519Sgblack@eecs.umich.edu { 2254519Sgblack@eecs.umich.edu buildMe(); 2264519Sgblack@eecs.umich.edu } 2274519Sgblack@eecs.umich.edu}}; 2284519Sgblack@eecs.umich.edu 2294519Sgblack@eecs.umich.edulet {{ 2304688Sgblack@eecs.umich.edu class X86MicroMeta(type): 2314688Sgblack@eecs.umich.edu def __new__(mcls, name, bases, dict): 2324688Sgblack@eecs.umich.edu abstract = False 2334688Sgblack@eecs.umich.edu if "abstract" in dict: 2344688Sgblack@eecs.umich.edu abstract = dict['abstract'] 2354688Sgblack@eecs.umich.edu del dict['abstract'] 2364688Sgblack@eecs.umich.edu 2374688Sgblack@eecs.umich.edu cls = type.__new__(mcls, name, bases, dict) 2384688Sgblack@eecs.umich.edu if not abstract: 2394688Sgblack@eecs.umich.edu allClasses[name] = cls 2404688Sgblack@eecs.umich.edu return cls 2414688Sgblack@eecs.umich.edu 2424688Sgblack@eecs.umich.edu class XXX86Microop(object): 2434688Sgblack@eecs.umich.edu __metaclass__ = X86MicroMeta 2444688Sgblack@eecs.umich.edu abstract = True 2454688Sgblack@eecs.umich.edu 2464528Sgblack@eecs.umich.edu class RegOp(X86Microop): 2474688Sgblack@eecs.umich.edu abstract = True 2484701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags, dataSize): 2494519Sgblack@eecs.umich.edu self.dest = dest 2504519Sgblack@eecs.umich.edu self.src1 = src1 2514519Sgblack@eecs.umich.edu self.src2 = src2 2524688Sgblack@eecs.umich.edu self.flags = flags 2534701Sgblack@eecs.umich.edu self.dataSize = dataSize 2544688Sgblack@eecs.umich.edu if flags is None: 2554688Sgblack@eecs.umich.edu self.ext = 0 2564688Sgblack@eecs.umich.edu else: 2574688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2584688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2594688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2604688Sgblack@eecs.umich.edu self.className += "Flags" 2614519Sgblack@eecs.umich.edu 2624519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2634560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2644539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(src2)s, %(dest)s, 2654688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2664519Sgblack@eecs.umich.edu "class_name" : self.className, 2674519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2684519Sgblack@eecs.umich.edu "src1" : self.src1, "src2" : self.src2, 2694519Sgblack@eecs.umich.edu "dest" : self.dest, 2704519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 2714519Sgblack@eecs.umich.edu "ext" : self.ext} 2724539Sgblack@eecs.umich.edu return allocator 2734519Sgblack@eecs.umich.edu 2744528Sgblack@eecs.umich.edu class RegOpImm(X86Microop): 2754688Sgblack@eecs.umich.edu abstract = True 2764701Sgblack@eecs.umich.edu def __init__(self, dest, src1, imm8, flags, dataSize): 2774519Sgblack@eecs.umich.edu self.dest = dest 2784519Sgblack@eecs.umich.edu self.src1 = src1 2794560Sgblack@eecs.umich.edu self.imm8 = imm8 2804688Sgblack@eecs.umich.edu self.flags = flags 2814701Sgblack@eecs.umich.edu self.dataSize = dataSize 2824688Sgblack@eecs.umich.edu if flags is None: 2834688Sgblack@eecs.umich.edu self.ext = 0 2844688Sgblack@eecs.umich.edu else: 2854688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2864688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2874688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2884688Sgblack@eecs.umich.edu self.className += "Flags" 2894519Sgblack@eecs.umich.edu 2904519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2914560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2924539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(imm8)s, %(dest)s, 2934688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2944519Sgblack@eecs.umich.edu "class_name" : self.className, 2954519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2964519Sgblack@eecs.umich.edu "src1" : self.src1, "imm8" : self.imm8, 2974519Sgblack@eecs.umich.edu "dest" : self.dest, 2984519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 2994519Sgblack@eecs.umich.edu "ext" : self.ext} 3004539Sgblack@eecs.umich.edu return allocator 3014519Sgblack@eecs.umich.edu}}; 3024519Sgblack@eecs.umich.edu 3034519Sgblack@eecs.umich.edulet {{ 3044519Sgblack@eecs.umich.edu 3054519Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 3064519Sgblack@eecs.umich.edu # them will always work. 3074519Sgblack@eecs.umich.edu header_output = "" 3084519Sgblack@eecs.umich.edu decoder_output = "" 3094519Sgblack@eecs.umich.edu exec_output = "" 3104519Sgblack@eecs.umich.edu 3114688Sgblack@eecs.umich.edu # A function which builds the C++ classes that implement the microops 3124714Sgblack@eecs.umich.edu def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"): 3134519Sgblack@eecs.umich.edu global header_output 3144519Sgblack@eecs.umich.edu global decoder_output 3154519Sgblack@eecs.umich.edu global exec_output 3164528Sgblack@eecs.umich.edu global microopClasses 3174595Sgblack@eecs.umich.edu 3184612Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, base, 3194612Sgblack@eecs.umich.edu {"code" : code, 3204688Sgblack@eecs.umich.edu "flag_code" : flagCode, 3214708Sgblack@eecs.umich.edu "cond_check" : condCheck, 3224708Sgblack@eecs.umich.edu "else_code" : elseCode}) 3234595Sgblack@eecs.umich.edu header_output += MicroRegOpDeclare.subst(iop) 3244595Sgblack@eecs.umich.edu decoder_output += MicroRegOpConstructor.subst(iop) 3254595Sgblack@eecs.umich.edu exec_output += MicroRegOpExecute.subst(iop) 3264595Sgblack@eecs.umich.edu 3274595Sgblack@eecs.umich.edu 3284688Sgblack@eecs.umich.edu checkCCFlagBits = "checkCondition(ccFlagBits)" 3294688Sgblack@eecs.umich.edu genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" 3304688Sgblack@eecs.umich.edu 3314688Sgblack@eecs.umich.edu 3324688Sgblack@eecs.umich.edu # This creates a python representations of a microop which are a cross 3334688Sgblack@eecs.umich.edu # product of reg/immediate and flag/no flag versions. 3344714Sgblack@eecs.umich.edu def defineMicroRegOp(mnemonic, code, subtract = False, cc=False, elseCode=";"): 3354519Sgblack@eecs.umich.edu Name = mnemonic 3364519Sgblack@eecs.umich.edu name = mnemonic.lower() 3374519Sgblack@eecs.umich.edu 3384519Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 3394519Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 3404519Sgblack@eecs.umich.edu # operand. 3414519Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3424519Sgblack@eecs.umich.edu regCode = matcher.sub("SrcReg2", code) 3434519Sgblack@eecs.umich.edu immCode = matcher.sub("imm8", code) 3444519Sgblack@eecs.umich.edu 3454714Sgblack@eecs.umich.edu if subtract: 3464714Sgblack@eecs.umich.edu secondSrc = "-op2, true" 3474714Sgblack@eecs.umich.edu else: 3484714Sgblack@eecs.umich.edu secondSrc = "op2" 3494714Sgblack@eecs.umich.edu 3504688Sgblack@eecs.umich.edu if not cc: 3514688Sgblack@eecs.umich.edu flagCode = genCCFlagBits % secondSrc 3524688Sgblack@eecs.umich.edu condCode = "true" 3534688Sgblack@eecs.umich.edu else: 3544688Sgblack@eecs.umich.edu flagCode = "" 3554688Sgblack@eecs.umich.edu condCode = checkCCFlagBits 3564688Sgblack@eecs.umich.edu 3574688Sgblack@eecs.umich.edu regFlagCode = matcher.sub("SrcReg2", flagCode) 3584688Sgblack@eecs.umich.edu immFlagCode = matcher.sub("imm8", flagCode) 3594688Sgblack@eecs.umich.edu 3604519Sgblack@eecs.umich.edu class RegOpChild(RegOp): 3614688Sgblack@eecs.umich.edu mnemonic = name 3624688Sgblack@eecs.umich.edu className = Name 3634701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 3644701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, flags, dataSize) 3654519Sgblack@eecs.umich.edu 3664688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 3674519Sgblack@eecs.umich.edu 3684714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 3694714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, 3704714Sgblack@eecs.umich.edu flagCode = regFlagCode, condCheck = condCode, elseCode = elseCode); 3714688Sgblack@eecs.umich.edu 3724595Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 3734688Sgblack@eecs.umich.edu mnemonic = name + 'i' 3744688Sgblack@eecs.umich.edu className = Name + 'Imm' 3754701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags=None, dataSize="env.dataSize"): 3764701Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__(dest, src1, src2, flags, dataSize) 3774519Sgblack@eecs.umich.edu 3784688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 3794519Sgblack@eecs.umich.edu 3804714Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode); 3814714Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, 3824714Sgblack@eecs.umich.edu flagCode = immFlagCode, condCheck = condCode, elseCode = elseCode); 3834688Sgblack@eecs.umich.edu 3844592Sgblack@eecs.umich.edu # This has it's own function because Wr ops have implicit destinations 3854708Sgblack@eecs.umich.edu def defineMicroRegOpWr(mnemonic, code, elseCode=";"): 3864592Sgblack@eecs.umich.edu Name = mnemonic 3874592Sgblack@eecs.umich.edu name = mnemonic.lower() 3884592Sgblack@eecs.umich.edu 3894592Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 3904592Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 3914592Sgblack@eecs.umich.edu # operand. 3924592Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3934592Sgblack@eecs.umich.edu regCode = matcher.sub("SrcReg2", code) 3944592Sgblack@eecs.umich.edu immCode = matcher.sub("imm8", code) 3954592Sgblack@eecs.umich.edu 3964592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 3974688Sgblack@eecs.umich.edu mnemonic = name 3984688Sgblack@eecs.umich.edu className = Name 3994701Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4004701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4014688Sgblack@eecs.umich.edu 4024688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4034688Sgblack@eecs.umich.edu 4044714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 4054714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, 4064714Sgblack@eecs.umich.edu condCheck = checkCCFlagBits, elseCode = elseCode); 4074688Sgblack@eecs.umich.edu 4084688Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 4094708Sgblack@eecs.umich.edu mnemonic = name + 'i' 4104708Sgblack@eecs.umich.edu className = Name + 'Imm' 4114701Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4124701Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4134592Sgblack@eecs.umich.edu 4144688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 4154592Sgblack@eecs.umich.edu 4164714Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode); 4174714Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, 4184714Sgblack@eecs.umich.edu condCheck = checkCCFlagBits, elseCode = elseCode); 4194592Sgblack@eecs.umich.edu 4204592Sgblack@eecs.umich.edu # This has it's own function because Rd ops don't always have two parameters 4214592Sgblack@eecs.umich.edu def defineMicroRegOpRd(mnemonic, code): 4224592Sgblack@eecs.umich.edu Name = mnemonic 4234592Sgblack@eecs.umich.edu name = mnemonic.lower() 4244592Sgblack@eecs.umich.edu 4254592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 4264701Sgblack@eecs.umich.edu def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 4274701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4284592Sgblack@eecs.umich.edu self.className = Name 4294592Sgblack@eecs.umich.edu self.mnemonic = name 4304592Sgblack@eecs.umich.edu 4314688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4324688Sgblack@eecs.umich.edu 4334714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 4344592Sgblack@eecs.umich.edu 4354595Sgblack@eecs.umich.edu def defineMicroRegOpImm(mnemonic, code): 4364595Sgblack@eecs.umich.edu Name = mnemonic 4374595Sgblack@eecs.umich.edu name = mnemonic.lower() 4384595Sgblack@eecs.umich.edu 4394595Sgblack@eecs.umich.edu class RegOpChild(RegOpImm): 4404701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 4414701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 4424595Sgblack@eecs.umich.edu self.className = Name 4434595Sgblack@eecs.umich.edu self.mnemonic = name 4444595Sgblack@eecs.umich.edu 4454688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4464688Sgblack@eecs.umich.edu 4474714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code); 4484595Sgblack@eecs.umich.edu 4494732Sgblack@eecs.umich.edu defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 4504732Sgblack@eecs.umich.edu defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 4514732Sgblack@eecs.umich.edu defineMicroRegOp('Adc', ''' 4524732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4534732Sgblack@eecs.umich.edu DestReg = merge(DestReg, SrcReg1 + op2 + flags.CF, dataSize); 4544732Sgblack@eecs.umich.edu ''') 4554732Sgblack@eecs.umich.edu defineMicroRegOp('Sbb', ''' 4564732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4574732Sgblack@eecs.umich.edu DestReg = merge(DestReg, SrcReg1 - op2 - flags.CF, dataSize); 4584732Sgblack@eecs.umich.edu ''', True) 4594732Sgblack@eecs.umich.edu defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 4604732Sgblack@eecs.umich.edu defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', True) 4614732Sgblack@eecs.umich.edu defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 4624732Sgblack@eecs.umich.edu # defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', True) 4634732Sgblack@eecs.umich.edu defineMicroRegOp('Mul1s', 'DestReg = merge(DestReg, DestReg * op2, dataSize)') 4644732Sgblack@eecs.umich.edu defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', 4654732Sgblack@eecs.umich.edu elseCode='DestReg=DestReg;', cc=True) 4664732Sgblack@eecs.umich.edu 4674732Sgblack@eecs.umich.edu # Shift instructions 4684732Sgblack@eecs.umich.edu defineMicroRegOp('Sll', ''' 4694732Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 4704732Sgblack@eecs.umich.edu DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize); 4714732Sgblack@eecs.umich.edu ''') 4724732Sgblack@eecs.umich.edu defineMicroRegOp('Srl', ''' 4734732Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 4744732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 4754732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 4764732Sgblack@eecs.umich.edu // to be sure they're zero. 4774732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 4784732Sgblack@eecs.umich.edu DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize); 4794732Sgblack@eecs.umich.edu ''') 4804732Sgblack@eecs.umich.edu defineMicroRegOp('Sra', ''' 4814732Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 4824732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 4834732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 4844732Sgblack@eecs.umich.edu // them manually to be sure. 4854732Sgblack@eecs.umich.edu uint64_t arithMask = 4864732Sgblack@eecs.umich.edu -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 4874732Sgblack@eecs.umich.edu DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) | arithMask, dataSize); 4884732Sgblack@eecs.umich.edu ''') 4894732Sgblack@eecs.umich.edu defineMicroRegOp('Ror', ''' 4904732Sgblack@eecs.umich.edu uint8_t shiftAmt = 4914732Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 4924732Sgblack@eecs.umich.edu if(shiftAmt) 4934732Sgblack@eecs.umich.edu { 4944732Sgblack@eecs.umich.edu uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt); 4954732Sgblack@eecs.umich.edu uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt); 4964732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 4974732Sgblack@eecs.umich.edu } 4984732Sgblack@eecs.umich.edu else 4994732Sgblack@eecs.umich.edu DestReg = DestReg; 5004732Sgblack@eecs.umich.edu ''') 5014732Sgblack@eecs.umich.edu defineMicroRegOp('Rcr', ''' 5024733Sgblack@eecs.umich.edu uint8_t shiftAmt = 5034733Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 5044733Sgblack@eecs.umich.edu if(shiftAmt) 5054733Sgblack@eecs.umich.edu { 5064733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5074733Sgblack@eecs.umich.edu uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); 5084733Sgblack@eecs.umich.edu if(shiftAmt > 1) 5094733Sgblack@eecs.umich.edu top |= SrcReg1 << (dataSize * 8 - shiftAmt - 1); 5104733Sgblack@eecs.umich.edu uint64_t bottom = bits(SrcReg1, dataSize * 8, shiftAmt); 5114733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5124733Sgblack@eecs.umich.edu } 5134733Sgblack@eecs.umich.edu else 5144733Sgblack@eecs.umich.edu DestReg = DestReg; 5154732Sgblack@eecs.umich.edu ''') 5164732Sgblack@eecs.umich.edu defineMicroRegOp('Rol', ''' 5174732Sgblack@eecs.umich.edu uint8_t shiftAmt = 5184732Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 5194732Sgblack@eecs.umich.edu if(shiftAmt) 5204732Sgblack@eecs.umich.edu { 5214732Sgblack@eecs.umich.edu uint64_t top = SrcReg1 << shiftAmt; 5224732Sgblack@eecs.umich.edu uint64_t bottom = 5234732Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 5244732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5254732Sgblack@eecs.umich.edu } 5264732Sgblack@eecs.umich.edu else 5274732Sgblack@eecs.umich.edu DestReg = DestReg; 5284732Sgblack@eecs.umich.edu ''') 5294732Sgblack@eecs.umich.edu defineMicroRegOp('Rcl', ''' 5304733Sgblack@eecs.umich.edu uint8_t shiftAmt = 5314733Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(4) : mask(3))); 5324733Sgblack@eecs.umich.edu if(shiftAmt) 5334733Sgblack@eecs.umich.edu { 5344733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5354733Sgblack@eecs.umich.edu uint64_t top = SrcReg1 << shiftAmt; 5364733Sgblack@eecs.umich.edu uint64_t bottom = flags.CF << (shiftAmt - 1); 5374733Sgblack@eecs.umich.edu if(shiftAmt > 1) 5384733Sgblack@eecs.umich.edu bottom |= 5394733Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1, 5404733Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 5414733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5424733Sgblack@eecs.umich.edu } 5434733Sgblack@eecs.umich.edu else 5444733Sgblack@eecs.umich.edu DestReg = DestReg; 5454732Sgblack@eecs.umich.edu ''') 5464732Sgblack@eecs.umich.edu 5474732Sgblack@eecs.umich.edu defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2', elseCode="RIP = RIP;") 5484732Sgblack@eecs.umich.edu 5494732Sgblack@eecs.umich.edu defineMicroRegOpRd('Rdip', 'DestReg = RIP') 5504732Sgblack@eecs.umich.edu 5514595Sgblack@eecs.umich.edu defineMicroRegOpImm('Sext', ''' 5524595Sgblack@eecs.umich.edu IntReg val = SrcReg1; 5534595Sgblack@eecs.umich.edu int sign_bit = bits(val, imm8-1, imm8-1); 5544595Sgblack@eecs.umich.edu val = sign_bit ? (val | ~mask(imm8)) : val; 5554595Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize);''') 5564714Sgblack@eecs.umich.edu 5574714Sgblack@eecs.umich.edu defineMicroRegOpImm('Zext', 'DestReg = bits(SrcReg1, imm8-1, 0);') 5584519Sgblack@eecs.umich.edu}}; 559