regop.isa revision 4688
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684519Sgblack@eecs.umich.edu %(op_decl)s; 694519Sgblack@eecs.umich.edu %(op_rd)s; 704688Sgblack@eecs.umich.edu 714688Sgblack@eecs.umich.edu if(%(cond_check)s) 724688Sgblack@eecs.umich.edu { 734688Sgblack@eecs.umich.edu %(code)s; 744688Sgblack@eecs.umich.edu %(flag_code)s; 754688Sgblack@eecs.umich.edu } 764519Sgblack@eecs.umich.edu 774519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 784519Sgblack@eecs.umich.edu if(fault == NoFault) 794519Sgblack@eecs.umich.edu { 804519Sgblack@eecs.umich.edu %(op_wb)s; 814519Sgblack@eecs.umich.edu } 824519Sgblack@eecs.umich.edu return fault; 834519Sgblack@eecs.umich.edu } 844519Sgblack@eecs.umich.edu}}; 854519Sgblack@eecs.umich.edu 864519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 874519Sgblack@eecs.umich.edu Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 884519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 894519Sgblack@eecs.umich.edu { 904519Sgblack@eecs.umich.edu Fault fault = NoFault; 914519Sgblack@eecs.umich.edu 924519Sgblack@eecs.umich.edu %(op_decl)s; 934519Sgblack@eecs.umich.edu %(op_rd)s; 944688Sgblack@eecs.umich.edu 954688Sgblack@eecs.umich.edu if(%(cond_check)s) 964688Sgblack@eecs.umich.edu { 974688Sgblack@eecs.umich.edu %(code)s; 984688Sgblack@eecs.umich.edu %(flag_code)s; 994688Sgblack@eecs.umich.edu } 1004519Sgblack@eecs.umich.edu 1014519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1024519Sgblack@eecs.umich.edu if(fault == NoFault) 1034519Sgblack@eecs.umich.edu { 1044519Sgblack@eecs.umich.edu %(op_wb)s; 1054519Sgblack@eecs.umich.edu } 1064519Sgblack@eecs.umich.edu return fault; 1074519Sgblack@eecs.umich.edu } 1084519Sgblack@eecs.umich.edu}}; 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1114519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu protected: 1144519Sgblack@eecs.umich.edu void buildMe(); 1154519Sgblack@eecs.umich.edu 1164519Sgblack@eecs.umich.edu public: 1174519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1184519Sgblack@eecs.umich.edu const char * instMnem, 1194519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1204519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1214688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext); 1224519Sgblack@eecs.umich.edu 1234519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1244519Sgblack@eecs.umich.edu const char * instMnem, 1254519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1264688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1334519Sgblack@eecs.umich.edu 1344519Sgblack@eecs.umich.edu class %(class_name)sImm : public %(base_class)s 1354519Sgblack@eecs.umich.edu { 1364519Sgblack@eecs.umich.edu protected: 1374519Sgblack@eecs.umich.edu void buildMe(); 1384519Sgblack@eecs.umich.edu 1394519Sgblack@eecs.umich.edu public: 1404519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1414519Sgblack@eecs.umich.edu const char * instMnem, 1424519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1434519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1444688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext); 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1474519Sgblack@eecs.umich.edu const char * instMnem, 1484519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1494688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext); 1504519Sgblack@eecs.umich.edu 1514519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1524519Sgblack@eecs.umich.edu }; 1534519Sgblack@eecs.umich.edu}}; 1544519Sgblack@eecs.umich.edu 1554519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1564519Sgblack@eecs.umich.edu 1574519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1584519Sgblack@eecs.umich.edu { 1594519Sgblack@eecs.umich.edu %(constructor)s; 1604519Sgblack@eecs.umich.edu } 1614519Sgblack@eecs.umich.edu 1624519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1634519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1644519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1654688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext) : 1664519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1674581Sgblack@eecs.umich.edu false, false, false, false, 1684688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1694581Sgblack@eecs.umich.edu %(op_class)s) 1704519Sgblack@eecs.umich.edu { 1714519Sgblack@eecs.umich.edu buildMe(); 1724519Sgblack@eecs.umich.edu } 1734519Sgblack@eecs.umich.edu 1744519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1754519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1764519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1774519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1784688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext) : 1794519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1804581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1814688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1824581Sgblack@eecs.umich.edu %(op_class)s) 1834519Sgblack@eecs.umich.edu { 1844519Sgblack@eecs.umich.edu buildMe(); 1854519Sgblack@eecs.umich.edu } 1864519Sgblack@eecs.umich.edu}}; 1874519Sgblack@eecs.umich.edu 1884519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1894519Sgblack@eecs.umich.edu 1904519Sgblack@eecs.umich.edu inline void %(class_name)sImm::buildMe() 1914519Sgblack@eecs.umich.edu { 1924519Sgblack@eecs.umich.edu %(constructor)s; 1934519Sgblack@eecs.umich.edu } 1944519Sgblack@eecs.umich.edu 1954519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 1964519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1974519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1984688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext) : 1994519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2004581Sgblack@eecs.umich.edu false, false, false, false, 2014688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2024581Sgblack@eecs.umich.edu %(op_class)s) 2034519Sgblack@eecs.umich.edu { 2044519Sgblack@eecs.umich.edu buildMe(); 2054519Sgblack@eecs.umich.edu } 2064519Sgblack@eecs.umich.edu 2074519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 2084519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2094519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2104519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2114688Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _ext) : 2124519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2134581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2144688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2154581Sgblack@eecs.umich.edu %(op_class)s) 2164519Sgblack@eecs.umich.edu { 2174519Sgblack@eecs.umich.edu buildMe(); 2184519Sgblack@eecs.umich.edu } 2194519Sgblack@eecs.umich.edu}}; 2204519Sgblack@eecs.umich.edu 2214519Sgblack@eecs.umich.edulet {{ 2224688Sgblack@eecs.umich.edu class X86MicroMeta(type): 2234688Sgblack@eecs.umich.edu def __new__(mcls, name, bases, dict): 2244688Sgblack@eecs.umich.edu abstract = False 2254688Sgblack@eecs.umich.edu if "abstract" in dict: 2264688Sgblack@eecs.umich.edu abstract = dict['abstract'] 2274688Sgblack@eecs.umich.edu del dict['abstract'] 2284688Sgblack@eecs.umich.edu 2294688Sgblack@eecs.umich.edu cls = type.__new__(mcls, name, bases, dict) 2304688Sgblack@eecs.umich.edu if not abstract: 2314688Sgblack@eecs.umich.edu allClasses[name] = cls 2324688Sgblack@eecs.umich.edu return cls 2334688Sgblack@eecs.umich.edu 2344688Sgblack@eecs.umich.edu class XXX86Microop(object): 2354688Sgblack@eecs.umich.edu __metaclass__ = X86MicroMeta 2364688Sgblack@eecs.umich.edu abstract = True 2374688Sgblack@eecs.umich.edu 2384528Sgblack@eecs.umich.edu class RegOp(X86Microop): 2394688Sgblack@eecs.umich.edu abstract = True 2404688Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags): 2414519Sgblack@eecs.umich.edu self.dest = dest 2424519Sgblack@eecs.umich.edu self.src1 = src1 2434519Sgblack@eecs.umich.edu self.src2 = src2 2444688Sgblack@eecs.umich.edu self.flags = flags 2454581Sgblack@eecs.umich.edu self.dataSize = "env.dataSize" 2464688Sgblack@eecs.umich.edu if flags is None: 2474688Sgblack@eecs.umich.edu self.ext = 0 2484688Sgblack@eecs.umich.edu else: 2494688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2504688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2514688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2524688Sgblack@eecs.umich.edu self.className += "Flags" 2534519Sgblack@eecs.umich.edu 2544519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2554560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2564539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(src2)s, %(dest)s, 2574688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2584519Sgblack@eecs.umich.edu "class_name" : self.className, 2594519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2604519Sgblack@eecs.umich.edu "src1" : self.src1, "src2" : self.src2, 2614519Sgblack@eecs.umich.edu "dest" : self.dest, 2624519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 2634519Sgblack@eecs.umich.edu "ext" : self.ext} 2644539Sgblack@eecs.umich.edu return allocator 2654519Sgblack@eecs.umich.edu 2664528Sgblack@eecs.umich.edu class RegOpImm(X86Microop): 2674688Sgblack@eecs.umich.edu abstract = True 2684688Sgblack@eecs.umich.edu def __init__(self, dest, src1, imm8, flags): 2694519Sgblack@eecs.umich.edu self.dest = dest 2704519Sgblack@eecs.umich.edu self.src1 = src1 2714560Sgblack@eecs.umich.edu self.imm8 = imm8 2724688Sgblack@eecs.umich.edu self.flags = flags 2734581Sgblack@eecs.umich.edu self.dataSize = "env.dataSize" 2744688Sgblack@eecs.umich.edu if flags is None: 2754688Sgblack@eecs.umich.edu self.ext = 0 2764688Sgblack@eecs.umich.edu else: 2774688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2784688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2794688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2804688Sgblack@eecs.umich.edu self.className += "Flags" 2814519Sgblack@eecs.umich.edu 2824519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2834560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2844539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(imm8)s, %(dest)s, 2854688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2864519Sgblack@eecs.umich.edu "class_name" : self.className, 2874519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2884519Sgblack@eecs.umich.edu "src1" : self.src1, "imm8" : self.imm8, 2894519Sgblack@eecs.umich.edu "dest" : self.dest, 2904519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 2914519Sgblack@eecs.umich.edu "ext" : self.ext} 2924539Sgblack@eecs.umich.edu return allocator 2934519Sgblack@eecs.umich.edu}}; 2944519Sgblack@eecs.umich.edu 2954519Sgblack@eecs.umich.edulet {{ 2964519Sgblack@eecs.umich.edu 2974519Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2984519Sgblack@eecs.umich.edu # them will always work. 2994519Sgblack@eecs.umich.edu header_output = "" 3004519Sgblack@eecs.umich.edu decoder_output = "" 3014519Sgblack@eecs.umich.edu exec_output = "" 3024519Sgblack@eecs.umich.edu 3034688Sgblack@eecs.umich.edu # A function which builds the C++ classes that implement the microops 3044688Sgblack@eecs.umich.edu def setUpMicroRegOp(name, Name, base, code, flagCode, condCheck): 3054519Sgblack@eecs.umich.edu global header_output 3064519Sgblack@eecs.umich.edu global decoder_output 3074519Sgblack@eecs.umich.edu global exec_output 3084528Sgblack@eecs.umich.edu global microopClasses 3094595Sgblack@eecs.umich.edu 3104612Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, base, 3114612Sgblack@eecs.umich.edu {"code" : code, 3124688Sgblack@eecs.umich.edu "flag_code" : flagCode, 3134688Sgblack@eecs.umich.edu "cond_check" : condCheck}) 3144595Sgblack@eecs.umich.edu header_output += MicroRegOpDeclare.subst(iop) 3154595Sgblack@eecs.umich.edu decoder_output += MicroRegOpConstructor.subst(iop) 3164595Sgblack@eecs.umich.edu exec_output += MicroRegOpExecute.subst(iop) 3174595Sgblack@eecs.umich.edu 3184595Sgblack@eecs.umich.edu 3194688Sgblack@eecs.umich.edu checkCCFlagBits = "checkCondition(ccFlagBits)" 3204688Sgblack@eecs.umich.edu genCCFlagBits = "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, SrcReg1, %s);" 3214688Sgblack@eecs.umich.edu 3224688Sgblack@eecs.umich.edu 3234688Sgblack@eecs.umich.edu # This creates a python representations of a microop which are a cross 3244688Sgblack@eecs.umich.edu # product of reg/immediate and flag/no flag versions. 3254688Sgblack@eecs.umich.edu def defineMicroRegOp(mnemonic, code, secondSrc = "op2", cc=False): 3264519Sgblack@eecs.umich.edu Name = mnemonic 3274519Sgblack@eecs.umich.edu name = mnemonic.lower() 3284519Sgblack@eecs.umich.edu 3294519Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 3304519Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 3314519Sgblack@eecs.umich.edu # operand. 3324519Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3334519Sgblack@eecs.umich.edu regCode = matcher.sub("SrcReg2", code) 3344519Sgblack@eecs.umich.edu immCode = matcher.sub("imm8", code) 3354519Sgblack@eecs.umich.edu 3364688Sgblack@eecs.umich.edu if not cc: 3374688Sgblack@eecs.umich.edu flagCode = genCCFlagBits % secondSrc 3384688Sgblack@eecs.umich.edu condCode = "true" 3394688Sgblack@eecs.umich.edu else: 3404688Sgblack@eecs.umich.edu flagCode = "" 3414688Sgblack@eecs.umich.edu condCode = checkCCFlagBits 3424688Sgblack@eecs.umich.edu 3434688Sgblack@eecs.umich.edu regFlagCode = matcher.sub("SrcReg2", flagCode) 3444688Sgblack@eecs.umich.edu immFlagCode = matcher.sub("imm8", flagCode) 3454688Sgblack@eecs.umich.edu 3464519Sgblack@eecs.umich.edu class RegOpChild(RegOp): 3474688Sgblack@eecs.umich.edu mnemonic = name 3484688Sgblack@eecs.umich.edu className = Name 3494688Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags=None): 3504688Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, flags) 3514519Sgblack@eecs.umich.edu 3524688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 3534519Sgblack@eecs.umich.edu 3544688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 3554688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, regFlagCode, condCode); 3564688Sgblack@eecs.umich.edu 3574595Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 3584688Sgblack@eecs.umich.edu mnemonic = name + 'i' 3594688Sgblack@eecs.umich.edu className = Name + 'Imm' 3604688Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags=None): 3614688Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__(dest, src1, src2, flags) 3624519Sgblack@eecs.umich.edu 3634688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 3644519Sgblack@eecs.umich.edu 3654688Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 3664688Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", immCode, immFlagCode, condCode); 3674688Sgblack@eecs.umich.edu 3684688Sgblack@eecs.umich.edu defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 3694688Sgblack@eecs.umich.edu defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 3704688Sgblack@eecs.umich.edu defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') 3714688Sgblack@eecs.umich.edu defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 3724688Sgblack@eecs.umich.edu defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 3734688Sgblack@eecs.umich.edu defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', '-op2') 3744688Sgblack@eecs.umich.edu defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 3754688Sgblack@eecs.umich.edu defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', '-op2') 3764688Sgblack@eecs.umich.edu defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', cc=True) 3774519Sgblack@eecs.umich.edu 3784592Sgblack@eecs.umich.edu # This has it's own function because Wr ops have implicit destinations 3794592Sgblack@eecs.umich.edu def defineMicroRegOpWr(mnemonic, code): 3804592Sgblack@eecs.umich.edu Name = mnemonic 3814592Sgblack@eecs.umich.edu name = mnemonic.lower() 3824592Sgblack@eecs.umich.edu 3834592Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 3844592Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 3854592Sgblack@eecs.umich.edu # operand. 3864592Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3874592Sgblack@eecs.umich.edu regCode = matcher.sub("SrcReg2", code) 3884592Sgblack@eecs.umich.edu immCode = matcher.sub("imm8", code) 3894592Sgblack@eecs.umich.edu 3904592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 3914688Sgblack@eecs.umich.edu mnemonic = name 3924688Sgblack@eecs.umich.edu className = Name 3934688Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None): 3944688Sgblack@eecs.umich.edu super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags) 3954688Sgblack@eecs.umich.edu 3964688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 3974688Sgblack@eecs.umich.edu 3984688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode, "", "true"); 3994688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, "", checkCCFlagBits); 4004688Sgblack@eecs.umich.edu 4014688Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 4024688Sgblack@eecs.umich.edu mnemonic = name 4034688Sgblack@eecs.umich.edu className = Name 4044592Sgblack@eecs.umich.edu def __init__(self, src1, src2): 4054688Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, None) 4064592Sgblack@eecs.umich.edu 4074688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 4084592Sgblack@eecs.umich.edu 4094688Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode, "", "true"); 4104688Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, "", checkCCFlagBits); 4114592Sgblack@eecs.umich.edu 4124592Sgblack@eecs.umich.edu defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2') 4134592Sgblack@eecs.umich.edu 4144592Sgblack@eecs.umich.edu # This has it's own function because Rd ops don't always have two parameters 4154592Sgblack@eecs.umich.edu def defineMicroRegOpRd(mnemonic, code): 4164592Sgblack@eecs.umich.edu Name = mnemonic 4174592Sgblack@eecs.umich.edu name = mnemonic.lower() 4184592Sgblack@eecs.umich.edu 4194592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 4204592Sgblack@eecs.umich.edu def __init__(self, dest, src1 = "NUM_INTREGS"): 4214688Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None) 4224592Sgblack@eecs.umich.edu self.className = Name 4234592Sgblack@eecs.umich.edu self.mnemonic = name 4244592Sgblack@eecs.umich.edu 4254688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4264688Sgblack@eecs.umich.edu 4274688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", code, "", "true"); 4284592Sgblack@eecs.umich.edu 4294592Sgblack@eecs.umich.edu defineMicroRegOpRd('Rdip', 'DestReg = RIP') 4304595Sgblack@eecs.umich.edu 4314595Sgblack@eecs.umich.edu def defineMicroRegOpImm(mnemonic, code): 4324595Sgblack@eecs.umich.edu Name = mnemonic 4334595Sgblack@eecs.umich.edu name = mnemonic.lower() 4344595Sgblack@eecs.umich.edu 4354595Sgblack@eecs.umich.edu class RegOpChild(RegOpImm): 4364595Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2): 4374688Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, None) 4384595Sgblack@eecs.umich.edu self.className = Name 4394595Sgblack@eecs.umich.edu self.mnemonic = name 4404595Sgblack@eecs.umich.edu 4414688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4424688Sgblack@eecs.umich.edu 4434688Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, "", "true"); 4444595Sgblack@eecs.umich.edu 4454595Sgblack@eecs.umich.edu defineMicroRegOpImm('Sext', ''' 4464595Sgblack@eecs.umich.edu IntReg val = SrcReg1; 4474595Sgblack@eecs.umich.edu int sign_bit = bits(val, imm8-1, imm8-1); 4484595Sgblack@eecs.umich.edu val = sign_bit ? (val | ~mask(imm8)) : val; 4494595Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize);''') 4504519Sgblack@eecs.umich.edu}}; 451