xref: /gem5/src/arch/x86/isa/microops/regop.isa

// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// Redistribution and use of this software in source and binary forms,
// with or without modification, are permitted provided that the
// following conditions are met:
//
// The software must be used only for Non-Commercial Use which means any
// use which is NOT directed to receiving any direct monetary
// compensation for, or commercial advantage from such use.  Illustrative
// examples of non-commercial use are academic research, personal study,
// teaching, education and corporate research & development.
// Illustrative examples of commercial use are distributing products for
// commercial advantage and providing services using the software for
// commercial advantage.
//
// If you wish to use this software or functionality therein that may be
// covered by patents for commercial use, please contact:
//     Director of Intellectual Property Licensing
//     Office of Strategy and Technology
//     Hewlett-Packard Company
//     1501 Page Mill Road
//     Palo Alto, California  94304
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.  Redistributions
// in binary form must reproduce the above copyright notice, this list of
// conditions and the following disclaimer in the documentation and/or
// other materials provided with the distribution.  Neither the name of
// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.  No right of
// sublicense is granted herewith.  Derivatives of the software and
// output created using the software may be prepared, but only for
// Non-Commercial Uses.  Derivatives of the software may be shared with
// others provided: (i) the others agree to abide by the list of
// conditions herein which includes the Non-Commercial Use restrictions;
// and (ii) such Derivatives of the software include the above copyright
// notice to acknowledge the contribution from this software where
// applicable, this list of conditions and the disclaimer below.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

//////////////////////////////////////////////////////////////////////////
//
// RegOp Microop templates
//
//////////////////////////////////////////////////////////////////////////

output header {{
    /**
     * Base classes for RegOps which provides a generateDisassembly method.
     */
    class RegOp : public X86MicroopBase
    {
      protected:
        const RegIndex src1;
        const RegIndex src2;
        const RegIndex dest;
        const bool setStatus;
        const uint8_t dataSize;
        const uint8_t ext;

        // Constructor
        RegOp(ExtMachInst _machInst,
                const char *mnem, const char *_instMnem,
                bool isMicro, bool isDelayed,
                bool isFirst, bool isLast,
                RegIndex _src1, RegIndex _src2, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
                OpClass __opClass) :
            X86MicroopBase(_machInst, mnem, _instMnem,
                    isMicro, isDelayed, isFirst, isLast,
                    __opClass),
            src1(_src1), src2(_src2), dest(_dest),
            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
        {
        }

        std::string generateDisassembly(Addr pc,
            const SymbolTable *symtab) const;
    };

    class RegOpImm : public X86MicroopBase
    {
      protected:
        const RegIndex src1;
        const uint8_t imm8;
        const RegIndex dest;
        const bool setStatus;
        const uint8_t dataSize;
        const uint8_t ext;

        // Constructor
        RegOpImm(ExtMachInst _machInst,
                const char * mnem, const char *_instMnem,
                bool isMicro, bool isDelayed,
                bool isFirst, bool isLast,
                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
                OpClass __opClass) :
            X86MicroopBase(_machInst, mnem, _instMnem,
                    isMicro, isDelayed, isFirst, isLast,
                    __opClass),
            src1(_src1), imm8(_imm8), dest(_dest),
            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
        {
        }

        std::string generateDisassembly(Addr pc,
            const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string RegOp::generateDisassembly(Addr pc,
            const SymbolTable *symtab) const
    {
        std::stringstream response;

        printMnemonic(response, instMnem, mnemonic);
        printReg(response, dest);
        response << ", ";
        printReg(response, src1);
        response << ", ";
        printReg(response, src2);
        return response.str();
    }

    std::string RegOpImm::generateDisassembly(Addr pc,
            const SymbolTable *symtab) const
    {
        std::stringstream response;

        printMnemonic(response, instMnem, mnemonic);
        printReg(response, dest);
        response << ", ";
        printReg(response, src1);
        ccprintf(response, ", %#x", imm8);
        return response.str();
    }
}};

def template MicroRegOpExecute {{
        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                Trace::InstRecord *traceData) const
        {
            Fault fault = NoFault;

            %(op_decl)s;
            %(op_rd)s;
            %(code)s;
            %(flag_code)s;

            //Write the resulting state to the execution context
            if(fault == NoFault)
            {
                %(op_wb)s;
            }
            return fault;
        }
}};

def template MicroRegOpImmExecute {{
        Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
                Trace::InstRecord *traceData) const
        {
            Fault fault = NoFault;

            %(op_decl)s;
            %(op_rd)s;
            %(code)s;
            %(flag_code)s;

            //Write the resulting state to the execution context
            if(fault == NoFault)
            {
                %(op_wb)s;
            }
            return fault;
        }
}};

def template MicroRegOpDeclare {{
    class %(class_name)s : public %(base_class)s
    {
      protected:
        void buildMe();

      public:
        %(class_name)s(ExtMachInst _machInst,
                const char * instMnem,
                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
                RegIndex _src1, RegIndex _src2, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext);

        %(class_name)s(ExtMachInst _machInst,
                const char * instMnem,
                RegIndex _src1, RegIndex _src2, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext);

        %(BasicExecDeclare)s
    };
}};

def template MicroRegOpImmDeclare {{

    class %(class_name)sImm : public %(base_class)s
    {
      protected:
        void buildMe();

      public:
        %(class_name)sImm(ExtMachInst _machInst,
                const char * instMnem,
                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext);

        %(class_name)sImm(ExtMachInst _machInst,
                const char * instMnem,
                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
                bool _setStatus, uint8_t _dataSize, uint8_t _ext);

        %(BasicExecDeclare)s
    };
}};

def template MicroRegOpConstructor {{

    inline void %(class_name)s::buildMe()
    {
        %(constructor)s;
    }

    inline %(class_name)s::%(class_name)s(
            ExtMachInst machInst, const char * instMnem,
            RegIndex _src1, RegIndex _src2, RegIndex _dest,
            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                false, false, false, false,
                _src1, _src2, _dest, _setStatus, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }

    inline %(class_name)s::%(class_name)s(
            ExtMachInst machInst, const char * instMnem,
            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
            RegIndex _src1, RegIndex _src2, RegIndex _dest,
            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                isMicro, isDelayed, isFirst, isLast,
                _src1, _src2, _dest, _setStatus, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }
}};

def template MicroRegOpImmConstructor {{

    inline void %(class_name)sImm::buildMe()
    {
        %(constructor)s;
    }

    inline %(class_name)sImm::%(class_name)sImm(
            ExtMachInst machInst, const char * instMnem,
            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                false, false, false, false,
                _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }

    inline %(class_name)sImm::%(class_name)sImm(
            ExtMachInst machInst, const char * instMnem,
            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                isMicro, isDelayed, isFirst, isLast,
                _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
                %(op_class)s)
    {
        buildMe();
    }
}};

let {{
    class RegOp(X86Microop):
        def __init__(self, dest, src1, src2, setStatus):
            self.dest = dest
            self.src1 = src1
            self.src2 = src2
            self.setStatus = setStatus
            self.dataSize = "env.dataSize"
            self.ext = 0

        def getAllocator(self, *microFlags):
            allocator = '''new %(class_name)s(machInst, mnemonic
                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
                    %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
                "class_name" : self.className,
                "flags" : self.microFlagsText(microFlags),
                "src1" : self.src1, "src2" : self.src2,
                "dest" : self.dest,
                "setStatus" : self.cppBool(self.setStatus),
                "dataSize" : self.dataSize,
                "ext" : self.ext}
            return allocator

    class RegOpImm(X86Microop):
        def __init__(self, dest, src1, imm8, setStatus):
            self.dest = dest
            self.src1 = src1
            self.imm8 = imm8
            self.setStatus = setStatus
            self.dataSize = "env.dataSize"
            self.ext = 0

        def getAllocator(self, *microFlags):
            allocator = '''new %(class_name)s(machInst, mnemonic
                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
                    %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
                "class_name" : self.className,
                "flags" : self.microFlagsText(microFlags),
                "src1" : self.src1, "imm8" : self.imm8,
                "dest" : self.dest,
                "setStatus" : self.cppBool(self.setStatus),
                "dataSize" : self.dataSize,
                "ext" : self.ext}
            return allocator
}};

let {{

    # Make these empty strings so that concatenating onto
    # them will always work.
    header_output = ""
    decoder_output = ""
    exec_output = ""

    def setUpMicroRegOp(name, Name, base, code, child, flagCode):
        global header_output
        global decoder_output
        global exec_output
        global microopClasses

        iop = InstObjParams(name, Name, base,
                {"code" : code,
                 "flag_code" : flagCode})
        header_output += MicroRegOpDeclare.subst(iop)
        decoder_output += MicroRegOpConstructor.subst(iop)
        exec_output += MicroRegOpExecute.subst(iop)

        microopClasses[name] = child

    def defineMicroRegOp(mnemonic, code, flagCode):
        Name = mnemonic
        name = mnemonic.lower()

        # Find op2 in each of the instruction definitions. Create two versions
        # of the code, one with an integer operand, and one with an immediate
        # operand.
        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
        regCode = matcher.sub("SrcReg2", code)
        immCode = matcher.sub("imm8", code)

        # Build the all register version of this micro op
        class RegOpChild(RegOp):
            def __init__(self, dest, src1, src2, setStatus=False):
                super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
                self.className = Name
                self.mnemonic = name

        setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);

        # Build the immediate version of this micro op
        class RegOpChildImm(RegOpImm):
            def __init__(self, dest, src1, src2, setStatus=False):
                super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
                self.className = Name + "Imm"
                self.mnemonic = name + "i"

        setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);

    defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
    defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
    defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
    defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
    defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
    defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
    defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
    defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
    defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")

    # This has it's own function because Wr ops have implicit destinations
    def defineMicroRegOpWr(mnemonic, code):
        Name = mnemonic
        name = mnemonic.lower()

        # Find op2 in each of the instruction definitions. Create two versions
        # of the code, one with an integer operand, and one with an immediate
        # operand.
        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
        regCode = matcher.sub("SrcReg2", code)
        immCode = matcher.sub("imm8", code)

        # Build the all register version of this micro op
        class RegOpChild(RegOp):
            def __init__(self, src1, src2):
                super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
                self.className = Name
                self.mnemonic = name

        setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");

        # Build the immediate version of this micro op
        class RegOpChildImm(RegOpImm):
            def __init__(self, src1, src2):
                super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
                self.className = Name + "Imm"
                self.mnemonic = name + "i"

        setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");

    defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')

    # This has it's own function because Rd ops don't always have two parameters
    def defineMicroRegOpRd(mnemonic, code):
        Name = mnemonic
        name = mnemonic.lower()

        class RegOpChild(RegOp):
            def __init__(self, dest, src1 = "NUM_INTREGS"):
                super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
                self.className = Name
                self.mnemonic = name

        setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");

    defineMicroRegOpRd('Rdip', 'DestReg = RIP')

    def defineMicroRegOpImm(mnemonic, code):
        Name = mnemonic
        name = mnemonic.lower()

        class RegOpChild(RegOpImm):
            def __init__(self, dest, src1, src2):
                super(RegOpChild, self).__init__(dest, src1, src2, False)
                self.className = Name
                self.mnemonic = name

        setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");

    defineMicroRegOpImm('Sext', '''
            IntReg val = SrcReg1;
            int sign_bit = bits(val, imm8-1, imm8-1);
            val = sign_bit ? (val | ~mask(imm8)) : val;
            DestReg = merge(DestReg, val, dataSize);''')
}};