regop.isa revision 4592
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534519Sgblack@eecs.umich.edu//
544519Sgblack@eecs.umich.edu// Authors: Gabe Black
554519Sgblack@eecs.umich.edu
564519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
574519Sgblack@eecs.umich.edu//
584519Sgblack@eecs.umich.edu// RegOp Microop templates
594519Sgblack@eecs.umich.edu//
604519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
614519Sgblack@eecs.umich.edu
624581Sgblack@eecs.umich.eduoutput header {{
634581Sgblack@eecs.umich.edu    /**
644581Sgblack@eecs.umich.edu     * Base classes for RegOps which provides a generateDisassembly method.
654581Sgblack@eecs.umich.edu     */
664581Sgblack@eecs.umich.edu    class RegOp : public X86MicroopBase
674581Sgblack@eecs.umich.edu    {
684581Sgblack@eecs.umich.edu      protected:
694581Sgblack@eecs.umich.edu        const RegIndex src1;
704581Sgblack@eecs.umich.edu        const RegIndex src2;
714581Sgblack@eecs.umich.edu        const RegIndex dest;
724581Sgblack@eecs.umich.edu        const bool setStatus;
734581Sgblack@eecs.umich.edu        const uint8_t dataSize;
744581Sgblack@eecs.umich.edu        const uint8_t ext;
754581Sgblack@eecs.umich.edu
764581Sgblack@eecs.umich.edu        // Constructor
774581Sgblack@eecs.umich.edu        RegOp(ExtMachInst _machInst,
784581Sgblack@eecs.umich.edu                const char *mnem, const char *_instMnem,
794581Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed,
804581Sgblack@eecs.umich.edu                bool isFirst, bool isLast,
814581Sgblack@eecs.umich.edu                RegIndex _src1, RegIndex _src2, RegIndex _dest,
824581Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
834581Sgblack@eecs.umich.edu                OpClass __opClass) :
844581Sgblack@eecs.umich.edu            X86MicroopBase(_machInst, mnem, _instMnem,
854581Sgblack@eecs.umich.edu                    isMicro, isDelayed, isFirst, isLast,
864581Sgblack@eecs.umich.edu                    __opClass),
874581Sgblack@eecs.umich.edu            src1(_src1), src2(_src2), dest(_dest),
884581Sgblack@eecs.umich.edu            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
894581Sgblack@eecs.umich.edu        {
904581Sgblack@eecs.umich.edu        }
914581Sgblack@eecs.umich.edu
924581Sgblack@eecs.umich.edu        std::string generateDisassembly(Addr pc,
934581Sgblack@eecs.umich.edu            const SymbolTable *symtab) const;
944581Sgblack@eecs.umich.edu    };
954581Sgblack@eecs.umich.edu
964581Sgblack@eecs.umich.edu    class RegOpImm : public X86MicroopBase
974581Sgblack@eecs.umich.edu    {
984581Sgblack@eecs.umich.edu      protected:
994581Sgblack@eecs.umich.edu        const RegIndex src1;
1004581Sgblack@eecs.umich.edu        const uint8_t imm8;
1014581Sgblack@eecs.umich.edu        const RegIndex dest;
1024581Sgblack@eecs.umich.edu        const bool setStatus;
1034581Sgblack@eecs.umich.edu        const uint8_t dataSize;
1044581Sgblack@eecs.umich.edu        const uint8_t ext;
1054581Sgblack@eecs.umich.edu
1064581Sgblack@eecs.umich.edu        // Constructor
1074581Sgblack@eecs.umich.edu        RegOpImm(ExtMachInst _machInst,
1084581Sgblack@eecs.umich.edu                const char * mnem, const char *_instMnem,
1094581Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed,
1104581Sgblack@eecs.umich.edu                bool isFirst, bool isLast,
1114581Sgblack@eecs.umich.edu                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
1124581Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext,
1134581Sgblack@eecs.umich.edu                OpClass __opClass) :
1144581Sgblack@eecs.umich.edu            X86MicroopBase(_machInst, mnem, _instMnem,
1154581Sgblack@eecs.umich.edu                    isMicro, isDelayed, isFirst, isLast,
1164581Sgblack@eecs.umich.edu                    __opClass),
1174581Sgblack@eecs.umich.edu            src1(_src1), imm8(_imm8), dest(_dest),
1184581Sgblack@eecs.umich.edu            setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
1194581Sgblack@eecs.umich.edu        {
1204581Sgblack@eecs.umich.edu        }
1214581Sgblack@eecs.umich.edu
1224581Sgblack@eecs.umich.edu        std::string generateDisassembly(Addr pc,
1234581Sgblack@eecs.umich.edu            const SymbolTable *symtab) const;
1244581Sgblack@eecs.umich.edu    };
1254581Sgblack@eecs.umich.edu}};
1264581Sgblack@eecs.umich.edu
1274581Sgblack@eecs.umich.eduoutput decoder {{
1284581Sgblack@eecs.umich.edu    std::string RegOp::generateDisassembly(Addr pc,
1294581Sgblack@eecs.umich.edu            const SymbolTable *symtab) const
1304581Sgblack@eecs.umich.edu    {
1314581Sgblack@eecs.umich.edu        std::stringstream response;
1324581Sgblack@eecs.umich.edu
1334581Sgblack@eecs.umich.edu        printMnemonic(response, instMnem, mnemonic);
1344581Sgblack@eecs.umich.edu        printReg(response, dest);
1354581Sgblack@eecs.umich.edu        response << ", ";
1364581Sgblack@eecs.umich.edu        printReg(response, src1);
1374581Sgblack@eecs.umich.edu        response << ", ";
1384581Sgblack@eecs.umich.edu        printReg(response, src2);
1394581Sgblack@eecs.umich.edu        return response.str();
1404581Sgblack@eecs.umich.edu    }
1414581Sgblack@eecs.umich.edu
1424581Sgblack@eecs.umich.edu    std::string RegOpImm::generateDisassembly(Addr pc,
1434581Sgblack@eecs.umich.edu            const SymbolTable *symtab) const
1444581Sgblack@eecs.umich.edu    {
1454581Sgblack@eecs.umich.edu        std::stringstream response;
1464581Sgblack@eecs.umich.edu
1474581Sgblack@eecs.umich.edu        printMnemonic(response, instMnem, mnemonic);
1484581Sgblack@eecs.umich.edu        printReg(response, dest);
1494581Sgblack@eecs.umich.edu        response << ", ";
1504581Sgblack@eecs.umich.edu        printReg(response, src1);
1514581Sgblack@eecs.umich.edu        ccprintf(response, ", %#x", imm8);
1524581Sgblack@eecs.umich.edu        return response.str();
1534581Sgblack@eecs.umich.edu    }
1544581Sgblack@eecs.umich.edu}};
1554581Sgblack@eecs.umich.edu
1564519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{
1574519Sgblack@eecs.umich.edu        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
1584519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
1594519Sgblack@eecs.umich.edu        {
1604519Sgblack@eecs.umich.edu            Fault fault = NoFault;
1614519Sgblack@eecs.umich.edu
1624519Sgblack@eecs.umich.edu            %(op_decl)s;
1634519Sgblack@eecs.umich.edu            %(op_rd)s;
1644519Sgblack@eecs.umich.edu            %(code)s;
1654519Sgblack@eecs.umich.edu
1664519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
1674519Sgblack@eecs.umich.edu            if(fault == NoFault)
1684519Sgblack@eecs.umich.edu            {
1694519Sgblack@eecs.umich.edu                %(op_wb)s;
1704519Sgblack@eecs.umich.edu            }
1714519Sgblack@eecs.umich.edu            return fault;
1724519Sgblack@eecs.umich.edu        }
1734519Sgblack@eecs.umich.edu}};
1744519Sgblack@eecs.umich.edu
1754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{
1764519Sgblack@eecs.umich.edu        Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
1774519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
1784519Sgblack@eecs.umich.edu        {
1794519Sgblack@eecs.umich.edu            Fault fault = NoFault;
1804519Sgblack@eecs.umich.edu
1814519Sgblack@eecs.umich.edu            %(op_decl)s;
1824519Sgblack@eecs.umich.edu            %(op_rd)s;
1834519Sgblack@eecs.umich.edu            %(code)s;
1844519Sgblack@eecs.umich.edu
1854519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
1864519Sgblack@eecs.umich.edu            if(fault == NoFault)
1874519Sgblack@eecs.umich.edu            {
1884519Sgblack@eecs.umich.edu                %(op_wb)s;
1894519Sgblack@eecs.umich.edu            }
1904519Sgblack@eecs.umich.edu            return fault;
1914519Sgblack@eecs.umich.edu        }
1924519Sgblack@eecs.umich.edu}};
1934519Sgblack@eecs.umich.edu
1944519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{
1954519Sgblack@eecs.umich.edu    class %(class_name)s : public %(base_class)s
1964519Sgblack@eecs.umich.edu    {
1974519Sgblack@eecs.umich.edu      protected:
1984519Sgblack@eecs.umich.edu        void buildMe();
1994519Sgblack@eecs.umich.edu
2004519Sgblack@eecs.umich.edu      public:
2014519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
2024519Sgblack@eecs.umich.edu                const char * instMnem,
2034519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2044519Sgblack@eecs.umich.edu                RegIndex _src1, RegIndex _src2, RegIndex _dest,
2054519Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext);
2064519Sgblack@eecs.umich.edu
2074519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
2084519Sgblack@eecs.umich.edu                const char * instMnem,
2094519Sgblack@eecs.umich.edu                RegIndex _src1, RegIndex _src2, RegIndex _dest,
2104519Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext);
2114519Sgblack@eecs.umich.edu
2124519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
2134519Sgblack@eecs.umich.edu    };
2144519Sgblack@eecs.umich.edu}};
2154519Sgblack@eecs.umich.edu
2164519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{
2174519Sgblack@eecs.umich.edu
2184519Sgblack@eecs.umich.edu    class %(class_name)sImm : public %(base_class)s
2194519Sgblack@eecs.umich.edu    {
2204519Sgblack@eecs.umich.edu      protected:
2214519Sgblack@eecs.umich.edu        void buildMe();
2224519Sgblack@eecs.umich.edu
2234519Sgblack@eecs.umich.edu      public:
2244519Sgblack@eecs.umich.edu        %(class_name)sImm(ExtMachInst _machInst,
2254519Sgblack@eecs.umich.edu                const char * instMnem,
2264519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2274519Sgblack@eecs.umich.edu                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
2284519Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext);
2294519Sgblack@eecs.umich.edu
2304519Sgblack@eecs.umich.edu        %(class_name)sImm(ExtMachInst _machInst,
2314519Sgblack@eecs.umich.edu                const char * instMnem,
2324519Sgblack@eecs.umich.edu                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
2334519Sgblack@eecs.umich.edu                bool _setStatus, uint8_t _dataSize, uint8_t _ext);
2344519Sgblack@eecs.umich.edu
2354519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
2364519Sgblack@eecs.umich.edu    };
2374519Sgblack@eecs.umich.edu}};
2384519Sgblack@eecs.umich.edu
2394519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{
2404519Sgblack@eecs.umich.edu
2414519Sgblack@eecs.umich.edu    inline void %(class_name)s::buildMe()
2424519Sgblack@eecs.umich.edu    {
2434519Sgblack@eecs.umich.edu        %(constructor)s;
2444519Sgblack@eecs.umich.edu    }
2454519Sgblack@eecs.umich.edu
2464519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2474519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2484519Sgblack@eecs.umich.edu            RegIndex _src1, RegIndex _src2, RegIndex _dest,
2494519Sgblack@eecs.umich.edu            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
2504519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2514581Sgblack@eecs.umich.edu                false, false, false, false,
2524581Sgblack@eecs.umich.edu                _src1, _src2, _dest, _setStatus, _dataSize, _ext,
2534581Sgblack@eecs.umich.edu                %(op_class)s)
2544519Sgblack@eecs.umich.edu    {
2554519Sgblack@eecs.umich.edu        buildMe();
2564519Sgblack@eecs.umich.edu    }
2574519Sgblack@eecs.umich.edu
2584519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2594519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2604519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2614519Sgblack@eecs.umich.edu            RegIndex _src1, RegIndex _src2, RegIndex _dest,
2624519Sgblack@eecs.umich.edu            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
2634519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2644581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
2654581Sgblack@eecs.umich.edu                _src1, _src2, _dest, _setStatus, _dataSize, _ext,
2664581Sgblack@eecs.umich.edu                %(op_class)s)
2674519Sgblack@eecs.umich.edu    {
2684519Sgblack@eecs.umich.edu        buildMe();
2694519Sgblack@eecs.umich.edu    }
2704519Sgblack@eecs.umich.edu}};
2714519Sgblack@eecs.umich.edu
2724519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{
2734519Sgblack@eecs.umich.edu
2744519Sgblack@eecs.umich.edu    inline void %(class_name)sImm::buildMe()
2754519Sgblack@eecs.umich.edu    {
2764519Sgblack@eecs.umich.edu        %(constructor)s;
2774519Sgblack@eecs.umich.edu    }
2784519Sgblack@eecs.umich.edu
2794519Sgblack@eecs.umich.edu    inline %(class_name)sImm::%(class_name)sImm(
2804519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2814519Sgblack@eecs.umich.edu            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
2824519Sgblack@eecs.umich.edu            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
2834519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2844581Sgblack@eecs.umich.edu                false, false, false, false,
2854581Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
2864581Sgblack@eecs.umich.edu                %(op_class)s)
2874519Sgblack@eecs.umich.edu    {
2884519Sgblack@eecs.umich.edu        buildMe();
2894519Sgblack@eecs.umich.edu    }
2904519Sgblack@eecs.umich.edu
2914519Sgblack@eecs.umich.edu    inline %(class_name)sImm::%(class_name)sImm(
2924519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2934519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2944519Sgblack@eecs.umich.edu            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
2954519Sgblack@eecs.umich.edu            bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
2964519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2974581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
2984581Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _setStatus, _dataSize, _ext,
2994581Sgblack@eecs.umich.edu                %(op_class)s)
3004519Sgblack@eecs.umich.edu    {
3014519Sgblack@eecs.umich.edu        buildMe();
3024519Sgblack@eecs.umich.edu    }
3034519Sgblack@eecs.umich.edu}};
3044519Sgblack@eecs.umich.edu
3054519Sgblack@eecs.umich.edulet {{
3064528Sgblack@eecs.umich.edu    class RegOp(X86Microop):
3074519Sgblack@eecs.umich.edu        def __init__(self, dest, src1, src2):
3084519Sgblack@eecs.umich.edu            self.dest = dest
3094519Sgblack@eecs.umich.edu            self.src1 = src1
3104519Sgblack@eecs.umich.edu            self.src2 = src2
3114519Sgblack@eecs.umich.edu            self.setStatus = False
3124581Sgblack@eecs.umich.edu            self.dataSize = "env.dataSize"
3134519Sgblack@eecs.umich.edu            self.ext = 0
3144519Sgblack@eecs.umich.edu
3154519Sgblack@eecs.umich.edu        def getAllocator(self, *microFlags):
3164560Sgblack@eecs.umich.edu            allocator = '''new %(class_name)s(machInst, mnemonic
3174539Sgblack@eecs.umich.edu                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
3184519Sgblack@eecs.umich.edu                    %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
3194519Sgblack@eecs.umich.edu                "class_name" : self.className,
3204519Sgblack@eecs.umich.edu                "flags" : self.microFlagsText(microFlags),
3214519Sgblack@eecs.umich.edu                "src1" : self.src1, "src2" : self.src2,
3224519Sgblack@eecs.umich.edu                "dest" : self.dest,
3234539Sgblack@eecs.umich.edu                "setStatus" : self.cppBool(self.setStatus),
3244519Sgblack@eecs.umich.edu                "dataSize" : self.dataSize,
3254519Sgblack@eecs.umich.edu                "ext" : self.ext}
3264539Sgblack@eecs.umich.edu            return allocator
3274519Sgblack@eecs.umich.edu
3284528Sgblack@eecs.umich.edu    class RegOpImm(X86Microop):
3294560Sgblack@eecs.umich.edu        def __init__(self, dest, src1, imm8):
3304519Sgblack@eecs.umich.edu            self.dest = dest
3314519Sgblack@eecs.umich.edu            self.src1 = src1
3324560Sgblack@eecs.umich.edu            self.imm8 = imm8
3334519Sgblack@eecs.umich.edu            self.setStatus = False
3344581Sgblack@eecs.umich.edu            self.dataSize = "env.dataSize"
3354519Sgblack@eecs.umich.edu            self.ext = 0
3364519Sgblack@eecs.umich.edu
3374519Sgblack@eecs.umich.edu        def getAllocator(self, *microFlags):
3384560Sgblack@eecs.umich.edu            allocator = '''new %(class_name)s(machInst, mnemonic
3394539Sgblack@eecs.umich.edu                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
3404519Sgblack@eecs.umich.edu                    %(setStatus)s, %(dataSize)s, %(ext)s)''' % {
3414519Sgblack@eecs.umich.edu                "class_name" : self.className,
3424519Sgblack@eecs.umich.edu                "flags" : self.microFlagsText(microFlags),
3434519Sgblack@eecs.umich.edu                "src1" : self.src1, "imm8" : self.imm8,
3444519Sgblack@eecs.umich.edu                "dest" : self.dest,
3454539Sgblack@eecs.umich.edu                "setStatus" : self.cppBool(self.setStatus),
3464519Sgblack@eecs.umich.edu                "dataSize" : self.dataSize,
3474519Sgblack@eecs.umich.edu                "ext" : self.ext}
3484539Sgblack@eecs.umich.edu            return allocator
3494519Sgblack@eecs.umich.edu}};
3504519Sgblack@eecs.umich.edu
3514519Sgblack@eecs.umich.edulet {{
3524519Sgblack@eecs.umich.edu
3534519Sgblack@eecs.umich.edu    # Make these empty strings so that concatenating onto
3544519Sgblack@eecs.umich.edu    # them will always work.
3554519Sgblack@eecs.umich.edu    header_output = ""
3564519Sgblack@eecs.umich.edu    decoder_output = ""
3574519Sgblack@eecs.umich.edu    exec_output = ""
3584519Sgblack@eecs.umich.edu
3594528Sgblack@eecs.umich.edu    def defineMicroRegOp(mnemonic, code):
3604519Sgblack@eecs.umich.edu        global header_output
3614519Sgblack@eecs.umich.edu        global decoder_output
3624519Sgblack@eecs.umich.edu        global exec_output
3634528Sgblack@eecs.umich.edu        global microopClasses
3644519Sgblack@eecs.umich.edu        Name = mnemonic
3654519Sgblack@eecs.umich.edu        name = mnemonic.lower()
3664519Sgblack@eecs.umich.edu
3674519Sgblack@eecs.umich.edu        # Find op2 in each of the instruction definitions. Create two versions
3684519Sgblack@eecs.umich.edu        # of the code, one with an integer operand, and one with an immediate
3694519Sgblack@eecs.umich.edu        # operand.
3704519Sgblack@eecs.umich.edu        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
3714519Sgblack@eecs.umich.edu        regCode = matcher.sub("SrcReg2", code)
3724519Sgblack@eecs.umich.edu        immCode = matcher.sub("imm8", code)
3734519Sgblack@eecs.umich.edu
3744519Sgblack@eecs.umich.edu        # Build up the all register version of this micro op
3754581Sgblack@eecs.umich.edu        iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode})
3764519Sgblack@eecs.umich.edu        header_output += MicroRegOpDeclare.subst(iop)
3774519Sgblack@eecs.umich.edu        decoder_output += MicroRegOpConstructor.subst(iop)
3784519Sgblack@eecs.umich.edu        exec_output += MicroRegOpExecute.subst(iop)
3794519Sgblack@eecs.umich.edu
3804519Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
3814519Sgblack@eecs.umich.edu            def __init__(self, dest, src1, src2):
3824528Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__(dest, src1, src2)
3834528Sgblack@eecs.umich.edu                self.className = Name
3844519Sgblack@eecs.umich.edu                self.mnemonic = name
3854519Sgblack@eecs.umich.edu
3864519Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
3874519Sgblack@eecs.umich.edu
3884519Sgblack@eecs.umich.edu        # Build up the immediate version of this micro op
3894519Sgblack@eecs.umich.edu        iop = InstObjParams(name + "i", Name,
3904581Sgblack@eecs.umich.edu                'RegOpImm', {"code" : immCode})
3914519Sgblack@eecs.umich.edu        header_output += MicroRegOpImmDeclare.subst(iop)
3924519Sgblack@eecs.umich.edu        decoder_output += MicroRegOpImmConstructor.subst(iop)
3934519Sgblack@eecs.umich.edu        exec_output += MicroRegOpImmExecute.subst(iop)
3944519Sgblack@eecs.umich.edu
3954519Sgblack@eecs.umich.edu        class RegOpImmChild(RegOpImm):
3964519Sgblack@eecs.umich.edu            def __init__(self, dest, src1, imm):
3974528Sgblack@eecs.umich.edu                super(RegOpImmChild, self).__init__(dest, src1, imm)
3984528Sgblack@eecs.umich.edu                self.className = Name + "Imm"
3994519Sgblack@eecs.umich.edu                self.mnemonic = name + "i"
4004519Sgblack@eecs.umich.edu
4014560Sgblack@eecs.umich.edu        microopClasses[name + "i"] = RegOpImmChild
4024519Sgblack@eecs.umich.edu
4034528Sgblack@eecs.umich.edu    defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
4044528Sgblack@eecs.umich.edu    defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
4054528Sgblack@eecs.umich.edu    defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
4064528Sgblack@eecs.umich.edu    defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
4074528Sgblack@eecs.umich.edu    defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
4084528Sgblack@eecs.umich.edu    defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
4094528Sgblack@eecs.umich.edu    defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
4104528Sgblack@eecs.umich.edu    defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
4114528Sgblack@eecs.umich.edu    defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
4124519Sgblack@eecs.umich.edu
4134592Sgblack@eecs.umich.edu    # This has it's own function because Wr ops have implicit destinations
4144592Sgblack@eecs.umich.edu    def defineMicroRegOpWr(mnemonic, code):
4154592Sgblack@eecs.umich.edu        global header_output
4164592Sgblack@eecs.umich.edu        global decoder_output
4174592Sgblack@eecs.umich.edu        global exec_output
4184592Sgblack@eecs.umich.edu        global microopClasses
4194592Sgblack@eecs.umich.edu        Name = mnemonic
4204592Sgblack@eecs.umich.edu        name = mnemonic.lower()
4214592Sgblack@eecs.umich.edu
4224592Sgblack@eecs.umich.edu        # Find op2 in each of the instruction definitions. Create two versions
4234592Sgblack@eecs.umich.edu        # of the code, one with an integer operand, and one with an immediate
4244592Sgblack@eecs.umich.edu        # operand.
4254592Sgblack@eecs.umich.edu        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
4264592Sgblack@eecs.umich.edu        regCode = matcher.sub("SrcReg2", code)
4274592Sgblack@eecs.umich.edu        immCode = matcher.sub("imm8", code)
4284592Sgblack@eecs.umich.edu
4294592Sgblack@eecs.umich.edu        # Build up the all register version of this micro op
4304592Sgblack@eecs.umich.edu        iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode})
4314592Sgblack@eecs.umich.edu        header_output += MicroRegOpDeclare.subst(iop)
4324592Sgblack@eecs.umich.edu        decoder_output += MicroRegOpConstructor.subst(iop)
4334592Sgblack@eecs.umich.edu        exec_output += MicroRegOpExecute.subst(iop)
4344592Sgblack@eecs.umich.edu
4354592Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
4364592Sgblack@eecs.umich.edu            def __init__(self, src1, src2):
4374592Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2)
4384592Sgblack@eecs.umich.edu                self.className = Name
4394592Sgblack@eecs.umich.edu                self.mnemonic = name
4404592Sgblack@eecs.umich.edu
4414592Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
4424592Sgblack@eecs.umich.edu
4434592Sgblack@eecs.umich.edu        # Build up the immediate version of this micro op
4444592Sgblack@eecs.umich.edu        iop = InstObjParams(name + "i", Name,
4454592Sgblack@eecs.umich.edu                'RegOpImm', {"code" : immCode})
4464592Sgblack@eecs.umich.edu        header_output += MicroRegOpImmDeclare.subst(iop)
4474592Sgblack@eecs.umich.edu        decoder_output += MicroRegOpImmConstructor.subst(iop)
4484592Sgblack@eecs.umich.edu        exec_output += MicroRegOpImmExecute.subst(iop)
4494592Sgblack@eecs.umich.edu
4504592Sgblack@eecs.umich.edu        class RegOpImmChild(RegOpImm):
4514592Sgblack@eecs.umich.edu            def __init__(self, src1, imm):
4524592Sgblack@eecs.umich.edu                super(RegOpImmChild, self).__init__("NUM_INTREGS", src1, imm)
4534592Sgblack@eecs.umich.edu                self.className = Name + "Imm"
4544592Sgblack@eecs.umich.edu                self.mnemonic = name + "i"
4554592Sgblack@eecs.umich.edu
4564592Sgblack@eecs.umich.edu        microopClasses[name + "i"] = RegOpImmChild
4574592Sgblack@eecs.umich.edu
4584592Sgblack@eecs.umich.edu    defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
4594592Sgblack@eecs.umich.edu
4604592Sgblack@eecs.umich.edu    # This has it's own function because Rd ops don't always have two parameters
4614592Sgblack@eecs.umich.edu    def defineMicroRegOpRd(mnemonic, code):
4624592Sgblack@eecs.umich.edu        global header_output
4634592Sgblack@eecs.umich.edu        global decoder_output
4644592Sgblack@eecs.umich.edu        global exec_output
4654592Sgblack@eecs.umich.edu        global microopClasses
4664592Sgblack@eecs.umich.edu        Name = mnemonic
4674592Sgblack@eecs.umich.edu        name = mnemonic.lower()
4684592Sgblack@eecs.umich.edu
4694592Sgblack@eecs.umich.edu        iop = InstObjParams(name, Name, 'RegOp', {"code" : code})
4704592Sgblack@eecs.umich.edu        header_output += MicroRegOpDeclare.subst(iop)
4714592Sgblack@eecs.umich.edu        decoder_output += MicroRegOpConstructor.subst(iop)
4724592Sgblack@eecs.umich.edu        exec_output += MicroRegOpExecute.subst(iop)
4734592Sgblack@eecs.umich.edu
4744592Sgblack@eecs.umich.edu        class RegOpChild(RegOp):
4754592Sgblack@eecs.umich.edu            def __init__(self, dest, src1 = "NUM_INTREGS"):
4764592Sgblack@eecs.umich.edu                super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS")
4774592Sgblack@eecs.umich.edu                self.className = Name
4784592Sgblack@eecs.umich.edu                self.mnemonic = name
4794592Sgblack@eecs.umich.edu
4804592Sgblack@eecs.umich.edu        microopClasses[name] = RegOpChild
4814592Sgblack@eecs.umich.edu
4824592Sgblack@eecs.umich.edu    defineMicroRegOpRd('Rdip', 'DestReg = RIP')
4834519Sgblack@eecs.umich.edu}};
484