regop.isa revision 12025
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 4510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 7610196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 13310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 14710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2329699Snilay@cs.wisc.edu flag_code, cond_check, else_code, cond_control_flag_init, 2339699Snilay@cs.wisc.edu op_class): 2345040Sgblack@eecs.umich.edu 2355040Sgblack@eecs.umich.edu # Globals to stick the output in 2365040Sgblack@eecs.umich.edu global header_output 2375040Sgblack@eecs.umich.edu global decoder_output 2385040Sgblack@eecs.umich.edu global exec_output 2395040Sgblack@eecs.umich.edu 2405040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 24111320Ssteve.reinhardt@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2427894SBrad.Beckmann@amd.com cond_control_flag_init)) 2437967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2447967Sgblack@eecs.umich.edu cond_control_flag_init)) 2455040Sgblack@eecs.umich.edu 2465040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2475040Sgblack@eecs.umich.edu # of this code. 2488588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2497967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2505062Sgblack@eecs.umich.edu if match: 2515062Sgblack@eecs.umich.edu typeQual = "" 2525062Sgblack@eecs.umich.edu if match.group("typeQual"): 2535062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2545062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2555040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2565062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2577967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2595062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2619699Snilay@cs.wisc.edu matcher.sub(src2_name, cond_control_flag_init), 2629699Snilay@cs.wisc.edu op_class) 2636647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2645040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2667967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2676647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2686647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2697894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2709699Snilay@cs.wisc.edu matcher.sub(imm_name, cond_control_flag_init), 2719699Snilay@cs.wisc.edu op_class) 2725040Sgblack@eecs.umich.edu return 2735040Sgblack@eecs.umich.edu 2745040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2755040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2765239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2775040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2789699Snilay@cs.wisc.edu code, big_code, "", "true", else_code, "", op_class) 2795040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2805040Sgblack@eecs.umich.edu 2815040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2825040Sgblack@eecs.umich.edu # compute it. 2837967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2847967Sgblack@eecs.umich.edu prefix = "" 2857967Sgblack@eecs.umich.edu for (rex, decl) in ( 2867967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2877967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2887967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2897967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2907967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2917967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2927967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2937967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2947967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2957967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2967967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2977967Sgblack@eecs.umich.edu if matcher.search(all): 2987967Sgblack@eecs.umich.edu prefix += decl + "\n" 2997967Sgblack@eecs.umich.edu if big: 3007967Sgblack@eecs.umich.edu if big_code != "": 3017967Sgblack@eecs.umich.edu big_code = prefix + big_code 3027967Sgblack@eecs.umich.edu else: 3037967Sgblack@eecs.umich.edu code = prefix + code 3045040Sgblack@eecs.umich.edu 3055040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3065040Sgblack@eecs.umich.edu 3075040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3085040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3095040Sgblack@eecs.umich.edu templates = regTemplates 3106647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3115040Sgblack@eecs.umich.edu if matcher.search(allCode): 3125040Sgblack@eecs.umich.edu base += "Imm" 3135040Sgblack@eecs.umich.edu templates = immTemplates 3145040Sgblack@eecs.umich.edu 3155040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3167967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3175040Sgblack@eecs.umich.edu {"code" : code, 3185040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3195040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3207894SBrad.Beckmann@amd.com "else_code" : else_code, 3219699Snilay@cs.wisc.edu "cond_control_flag_init" : cond_control_flag_init, 3229699Snilay@cs.wisc.edu "op_class" : op_class})] 3237967Sgblack@eecs.umich.edu if big_code != "": 3247967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3257967Sgblack@eecs.umich.edu {"code" : big_code, 3267967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3277967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3287967Sgblack@eecs.umich.edu "else_code" : else_code, 3299699Snilay@cs.wisc.edu "cond_control_flag_init" : cond_control_flag_init, 3309699Snilay@cs.wisc.edu "op_class" : op_class})] 3315040Sgblack@eecs.umich.edu 3325040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3337967Sgblack@eecs.umich.edu for iop in iops: 3347967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3357967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3367967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3375040Sgblack@eecs.umich.edu 3385040Sgblack@eecs.umich.edu 3395040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3404688Sgblack@eecs.umich.edu abstract = False 3415040Sgblack@eecs.umich.edu name = Name.lower() 3424688Sgblack@eecs.umich.edu if "abstract" in dict: 3434688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3444688Sgblack@eecs.umich.edu del dict['abstract'] 3454688Sgblack@eecs.umich.edu 3465040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3474688Sgblack@eecs.umich.edu if not abstract: 3485040Sgblack@eecs.umich.edu cls.className = Name 3495040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3505040Sgblack@eecs.umich.edu code = cls.code 3517967Sgblack@eecs.umich.edu big_code = cls.big_code 3525040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3535040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3545040Sgblack@eecs.umich.edu else_code = cls.else_code 3557894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3569699Snilay@cs.wisc.edu op_class = cls.op_class 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Set up the C++ classes 3597967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3607967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3619699Snilay@cs.wisc.edu cond_control_flag_init, op_class) 3625040Sgblack@eecs.umich.edu 3635040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3645040Sgblack@eecs.umich.edu global microopClasses 3655040Sgblack@eecs.umich.edu microopClasses[name] = cls 3665040Sgblack@eecs.umich.edu 3677894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3687894SBrad.Beckmann@amd.com cond_control_flag_init)) 3695040Sgblack@eecs.umich.edu 3705040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3715040Sgblack@eecs.umich.edu # of this code. 3728588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3735040Sgblack@eecs.umich.edu if matcher.search(allCode): 3745040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3754688Sgblack@eecs.umich.edu return cls 3764688Sgblack@eecs.umich.edu 3775040Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3795040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3805040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3814688Sgblack@eecs.umich.edu abstract = True 3824688Sgblack@eecs.umich.edu 3835040Sgblack@eecs.umich.edu # Default template parameter values 3847967Sgblack@eecs.umich.edu big_code = "" 3855040Sgblack@eecs.umich.edu flag_code = "" 3865040Sgblack@eecs.umich.edu cond_check = "true" 3875040Sgblack@eecs.umich.edu else_code = ";" 3887894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3899699Snilay@cs.wisc.edu op_class = "IntAluOp" 3905040Sgblack@eecs.umich.edu 3915040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3924519Sgblack@eecs.umich.edu self.dest = dest 3934519Sgblack@eecs.umich.edu self.src1 = src1 3945040Sgblack@eecs.umich.edu self.op2 = op2 3954688Sgblack@eecs.umich.edu self.flags = flags 3964701Sgblack@eecs.umich.edu self.dataSize = dataSize 3974688Sgblack@eecs.umich.edu if flags is None: 3984688Sgblack@eecs.umich.edu self.ext = 0 3994688Sgblack@eecs.umich.edu else: 4004688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4014688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4024688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4034688Sgblack@eecs.umich.edu self.className += "Flags" 4044519Sgblack@eecs.umich.edu 4057620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4067967Sgblack@eecs.umich.edu if self.big_code != "": 4077967Sgblack@eecs.umich.edu className = self.className 4087967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4097967Sgblack@eecs.umich.edu className += "Imm" 4107967Sgblack@eecs.umich.edu allocString = ''' 4117967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4127967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4137967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4147967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4157967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4167967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4177967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4187967Sgblack@eecs.umich.edu ''' 4197967Sgblack@eecs.umich.edu allocator = allocString % { 4207967Sgblack@eecs.umich.edu "class_name" : className, 4217967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4227967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4237967Sgblack@eecs.umich.edu "dest" : self.dest, 4247967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4257967Sgblack@eecs.umich.edu "ext" : self.ext} 4267967Sgblack@eecs.umich.edu return allocator 4277967Sgblack@eecs.umich.edu else: 4287967Sgblack@eecs.umich.edu className = self.className 4297967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4307967Sgblack@eecs.umich.edu className += "Imm" 4317967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4327967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4337967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4347967Sgblack@eecs.umich.edu "class_name" : className, 4357967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4367967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4377967Sgblack@eecs.umich.edu "dest" : self.dest, 4387967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4397967Sgblack@eecs.umich.edu "ext" : self.ext} 4407967Sgblack@eecs.umich.edu return allocator 4414519Sgblack@eecs.umich.edu 4425040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4434688Sgblack@eecs.umich.edu abstract = True 4445040Sgblack@eecs.umich.edu flag_code = ''' 4455040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4465115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4479212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 4489212Snilay@cs.wisc.edu PredezfBit, ext & ~mask, result, psrc1, op2); 4499212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4509212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4519212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4529010Snilay@cs.wisc.edu 4535040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4549212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~((CFBit | OFBit) & ext); 4559212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ECFBit & ext); 4565040Sgblack@eecs.umich.edu ''' 4574519Sgblack@eecs.umich.edu 4585040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4595040Sgblack@eecs.umich.edu abstract = True 4609010Snilay@cs.wisc.edu flag_code = ''' 4619212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4629212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4639212Snilay@cs.wisc.edu ext, result, psrc1, op2); 4649212Snilay@cs.wisc.edu 4659212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4669212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4679212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4689212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4699212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4709010Snilay@cs.wisc.edu ''' 4714519Sgblack@eecs.umich.edu 4725040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4735040Sgblack@eecs.umich.edu abstract = True 4749010Snilay@cs.wisc.edu flag_code = ''' 4759212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4769212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4779212Snilay@cs.wisc.edu ext, result, psrc1, ~op2, true); 4789212Snilay@cs.wisc.edu 4799212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4809212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4819212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4829212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4839212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4849010Snilay@cs.wisc.edu ''' 4854519Sgblack@eecs.umich.edu 4865040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4875040Sgblack@eecs.umich.edu abstract = True 4889211Snilay@cs.wisc.edu cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \ 4899211Snilay@cs.wisc.edu ezfBit, ext)" 4907894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4914519Sgblack@eecs.umich.edu 4925063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4935063Sgblack@eecs.umich.edu abstract = True 4945063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4955063Sgblack@eecs.umich.edu if not src1: 4965063Sgblack@eecs.umich.edu src1 = dest 4976345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4986345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4995063Sgblack@eecs.umich.edu 5005063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 5015063Sgblack@eecs.umich.edu abstract = True 5025063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 5036345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 5046345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 5055063Sgblack@eecs.umich.edu 5065040Sgblack@eecs.umich.edu class Add(FlagRegOp): 5077969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 5087969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 5094595Sgblack@eecs.umich.edu 5105040Sgblack@eecs.umich.edu class Or(LogicRegOp): 5117969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 5127969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 5134595Sgblack@eecs.umich.edu 5145040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5155040Sgblack@eecs.umich.edu code = ''' 5169010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5177969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 5185040Sgblack@eecs.umich.edu ''' 5197967Sgblack@eecs.umich.edu big_code = ''' 5209010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5217969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 5227967Sgblack@eecs.umich.edu ''' 5235040Sgblack@eecs.umich.edu 5245040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5255040Sgblack@eecs.umich.edu code = ''' 5269010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5277969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 5285040Sgblack@eecs.umich.edu ''' 5297967Sgblack@eecs.umich.edu big_code = ''' 5309010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5317969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5327967Sgblack@eecs.umich.edu ''' 5335040Sgblack@eecs.umich.edu 5345040Sgblack@eecs.umich.edu class And(LogicRegOp): 5357969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5367969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5375040Sgblack@eecs.umich.edu 5385040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5397969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5407969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5415040Sgblack@eecs.umich.edu 5425040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5437969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5447969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5455040Sgblack@eecs.umich.edu 5465063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5479699Snilay@cs.wisc.edu op_class = 'IntMultOp' 5489699Snilay@cs.wisc.edu 54912025Sgabeblack@google.com # Multiply two values Aa and Bb where Aa = A << p + a, then correct for 55012025Sgabeblack@google.com # negative operands. 55112025Sgabeblack@google.com # Aa * Bb 55212025Sgabeblack@google.com # = (A << p + a) * (B << p + b) 55312025Sgabeblack@google.com # = (A * B) << 2p + (A * b + a * B) << p + a * b 5545040Sgblack@eecs.umich.edu code = ''' 5555063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 55612025Sgabeblack@google.com 55712025Sgabeblack@google.com int p = (dataSize * 8) / 2; 55812025Sgabeblack@google.com uint64_t A = bits(psrc1, 2 * p - 1, p); 55912025Sgabeblack@google.com uint64_t a = bits(psrc1, p - 1, 0); 56012025Sgabeblack@google.com uint64_t B = bits<uint64_t>(op2, 2 * p - 1, p); 56112025Sgabeblack@google.com uint64_t b = bits<uint64_t>(op2, p - 1, 0); 56212025Sgabeblack@google.com 56312025Sgabeblack@google.com uint64_t c1, c2; // Carry between place values. 56412025Sgabeblack@google.com uint64_t ab = a * b, Ab = A * b, aB = a * B, AB = A * B; 56512025Sgabeblack@google.com 56612025Sgabeblack@google.com c1 = ab >> p; 56712025Sgabeblack@google.com 56812025Sgabeblack@google.com // Be careful to avoid overflow if p is large. 56912025Sgabeblack@google.com if (p == 32) { 57012025Sgabeblack@google.com c2 = (c1 >> 1) + (Ab >> 1) + (aB >> 1); 57112025Sgabeblack@google.com c2 += ((c1 & 0x1) + (Ab & 0x1) + (aB & 0x1)) >> 1; 57212025Sgabeblack@google.com c2 >>= (p - 1); 57312025Sgabeblack@google.com } else { 57412025Sgabeblack@google.com c2 = (c1 + Ab + aB) >> p; 57512025Sgabeblack@google.com } 57612025Sgabeblack@google.com 57712025Sgabeblack@google.com uint64_t hi = AB + c2; 57812025Sgabeblack@google.com 5796462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 58012025Sgabeblack@google.com hi -= op2; 5816462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 58212025Sgabeblack@google.com hi -= psrc1; 58312025Sgabeblack@google.com 58412025Sgabeblack@google.com ProdHi = hi; 5855040Sgblack@eecs.umich.edu ''' 5866463Sgblack@eecs.umich.edu flag_code = ''' 5876463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5886463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5899212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 5909212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 5916463Sgblack@eecs.umich.edu } else { 5929212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 5939212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 5946463Sgblack@eecs.umich.edu } 5956463Sgblack@eecs.umich.edu ''' 5965040Sgblack@eecs.umich.edu 5975063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5989699Snilay@cs.wisc.edu op_class = 'IntMultOp' 5999699Snilay@cs.wisc.edu 60012025Sgabeblack@google.com # Multiply two values Aa and Bb where Aa = A << p + a. 60112025Sgabeblack@google.com # Aa * Bb 60212025Sgabeblack@google.com # = (A << p + a) * (B << p + b) 60312025Sgabeblack@google.com # = (A * B) << 2p + (A * b + a * B) << p + a * b 6045040Sgblack@eecs.umich.edu code = ''' 6055063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 60612025Sgabeblack@google.com 60712025Sgabeblack@google.com int p = (dataSize * 8) / 2; 60812025Sgabeblack@google.com uint64_t A = bits(psrc1, 2 * p - 1, p); 60912025Sgabeblack@google.com uint64_t a = bits(psrc1, p - 1, 0); 61012025Sgabeblack@google.com uint64_t B = bits<uint64_t>(op2, 2 * p - 1, p); 61112025Sgabeblack@google.com uint64_t b = bits<uint64_t>(op2, p - 1, 0); 61212025Sgabeblack@google.com 61312025Sgabeblack@google.com uint64_t c1, c2; // Carry between place values. 61412025Sgabeblack@google.com uint64_t ab = a * b, Ab = A * b, aB = a * B, AB = A * B; 61512025Sgabeblack@google.com 61612025Sgabeblack@google.com c1 = ab >> p; 61712025Sgabeblack@google.com 61812025Sgabeblack@google.com // Be careful to avoid overflow if p is large. 61912025Sgabeblack@google.com if (p == 32) { 62012025Sgabeblack@google.com c2 = (c1 >> 1) + (Ab >> 1) + (aB >> 1); 62112025Sgabeblack@google.com c2 += ((c1 & 0x1) + (Ab & 0x1) + (aB & 0x1)) >> 1; 62212025Sgabeblack@google.com c2 >>= (p - 1); 62312025Sgabeblack@google.com } else { 62412025Sgabeblack@google.com c2 = (c1 + Ab + aB) >> p; 62512025Sgabeblack@google.com } 62612025Sgabeblack@google.com 62712025Sgabeblack@google.com ProdHi = AB + c2; 6285040Sgblack@eecs.umich.edu ''' 6296463Sgblack@eecs.umich.edu flag_code = ''' 6306463Sgblack@eecs.umich.edu if (ProdHi) { 6319212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 6329212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 6336463Sgblack@eecs.umich.edu } else { 6349212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 6359212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 6366463Sgblack@eecs.umich.edu } 6376463Sgblack@eecs.umich.edu ''' 6385040Sgblack@eecs.umich.edu 6395063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 6405063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 6417967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 6425040Sgblack@eecs.umich.edu 6435063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 6445063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 6455063Sgblack@eecs.umich.edu if not src1: 6465063Sgblack@eecs.umich.edu src1 = dest 6476345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 6486345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 6495063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 6507967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 6515062Sgblack@eecs.umich.edu 6525075Sgblack@eecs.umich.edu # One or two bit divide 6535075Sgblack@eecs.umich.edu class Div1(WrRegOp): 6549699Snilay@cs.wisc.edu op_class = 'IntDivOp' 6559699Snilay@cs.wisc.edu 6565040Sgblack@eecs.umich.edu code = ''' 6575075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 6585075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 6595075Sgblack@eecs.umich.edu uint64_t quotient = 0; 6605075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 6615075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 6625075Sgblack@eecs.umich.edu //a source. 6635075Sgblack@eecs.umich.edu uint64_t divisor = op2; 6645075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 6655075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 6665075Sgblack@eecs.umich.edu //Do the division. 6677719Sgblack@eecs.umich.edu if (divisor == 0) { 66810805Snilay@cs.wisc.edu fault = std::make_shared<DivideError>(); 6697719Sgblack@eecs.umich.edu } else { 6707719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6717719Sgblack@eecs.umich.edu //Record the final results. 6727719Sgblack@eecs.umich.edu Remainder = remainder; 6737719Sgblack@eecs.umich.edu Quotient = quotient; 6747719Sgblack@eecs.umich.edu Divisor = divisor; 6757719Sgblack@eecs.umich.edu } 6765040Sgblack@eecs.umich.edu ''' 6774823Sgblack@eecs.umich.edu 6785075Sgblack@eecs.umich.edu # Step divide 6795075Sgblack@eecs.umich.edu class Div2(RegOp): 6809699Snilay@cs.wisc.edu op_class = 'IntDivOp' 6819699Snilay@cs.wisc.edu 6827967Sgblack@eecs.umich.edu divCode = ''' 6835075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6845075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6855075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6865075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6875075Sgblack@eecs.umich.edu int remaining = op2; 6885075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6895075Sgblack@eecs.umich.edu //little. 6907719Sgblack@eecs.umich.edu if (divisor == 0) { 69110805Snilay@cs.wisc.edu fault = std::make_shared<DivideError>(); 6927719Sgblack@eecs.umich.edu } else if (remaining) { 6937070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6947070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6957070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6967070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6977070Sgblack@eecs.umich.edu quotient <<= 1; 6987070Sgblack@eecs.umich.edu remaining--; 6997070Sgblack@eecs.umich.edu } 7007070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 7017080Sgblack@eecs.umich.edu bool highBit = false; 7027070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 7037080Sgblack@eecs.umich.edu highBit = true; 7047070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 7057070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 7067070Sgblack@eecs.umich.edu quotient <<= 1; 7077070Sgblack@eecs.umich.edu remaining--; 7087070Sgblack@eecs.umich.edu } 7097080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 7107080Sgblack@eecs.umich.edu quotient++; 7117080Sgblack@eecs.umich.edu dividend -= divisor; 7127080Sgblack@eecs.umich.edu } 7137070Sgblack@eecs.umich.edu } 7147070Sgblack@eecs.umich.edu remainder = dividend; 7157070Sgblack@eecs.umich.edu } else { 7167070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 7177070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 7187070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 7197070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 7207070Sgblack@eecs.umich.edu quotient <<= 1; 7217070Sgblack@eecs.umich.edu remaining--; 7227070Sgblack@eecs.umich.edu } 7237070Sgblack@eecs.umich.edu remainder = dividend; 7247070Sgblack@eecs.umich.edu //Do the division. 7257070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 7265075Sgblack@eecs.umich.edu } 7275075Sgblack@eecs.umich.edu } 7285075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 7297967Sgblack@eecs.umich.edu %s 7305075Sgblack@eecs.umich.edu //Record the final results 7315075Sgblack@eecs.umich.edu Remainder = remainder; 7325075Sgblack@eecs.umich.edu Quotient = quotient; 7335075Sgblack@eecs.umich.edu ''' 7347967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 7357967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 7365075Sgblack@eecs.umich.edu flag_code = ''' 7377480Sgblack@eecs.umich.edu if (remaining == 0) 7389212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 7395075Sgblack@eecs.umich.edu else 7409212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 7415075Sgblack@eecs.umich.edu ''' 7424732Sgblack@eecs.umich.edu 7435075Sgblack@eecs.umich.edu class Divq(RdRegOp): 7445075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 7457967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 7465075Sgblack@eecs.umich.edu 7475075Sgblack@eecs.umich.edu class Divr(RdRegOp): 7485075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 7497967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 7505040Sgblack@eecs.umich.edu 7515040Sgblack@eecs.umich.edu class Mov(CondRegOp): 7525040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 7536482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 7545040Sgblack@eecs.umich.edu 7554732Sgblack@eecs.umich.edu # Shift instructions 7565040Sgblack@eecs.umich.edu 7575076Sgblack@eecs.umich.edu class Sll(RegOp): 7585040Sgblack@eecs.umich.edu code = ''' 7594756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7604823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 7615040Sgblack@eecs.umich.edu ''' 7627967Sgblack@eecs.umich.edu big_code = ''' 7637967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7647967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 7657967Sgblack@eecs.umich.edu ''' 7665076Sgblack@eecs.umich.edu flag_code = ''' 7675076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7685076Sgblack@eecs.umich.edu if (shiftAmt) { 7695076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7705076Sgblack@eecs.umich.edu //worry about setting them. 7719212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 7729212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 7739010Snilay@cs.wisc.edu 7745076Sgblack@eecs.umich.edu int CFBits = 0; 7755076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 7766441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 7776441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 7785076Sgblack@eecs.umich.edu CFBits = 1; 7796441Sgblack@eecs.umich.edu } 7809010Snilay@cs.wisc.edu 7815076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7829010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 7839212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 7849212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 7859010Snilay@cs.wisc.edu } 7869010Snilay@cs.wisc.edu 7875076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7885076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7899212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 7909010Snilay@cs.wisc.edu 7915076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7929212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 7939212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 7949212Snilay@cs.wisc.edu DestReg, psrc1, op2); 7959212Snilay@cs.wisc.edu 7969212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 7979212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 7989212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 7995076Sgblack@eecs.umich.edu } 8005076Sgblack@eecs.umich.edu ''' 8015040Sgblack@eecs.umich.edu 8025076Sgblack@eecs.umich.edu class Srl(RegOp): 8037967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 8047967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 8057967Sgblack@eecs.umich.edu # to be sure they're zero. 8065040Sgblack@eecs.umich.edu code = ''' 8074756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8084732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 8094823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 8105040Sgblack@eecs.umich.edu ''' 8117967Sgblack@eecs.umich.edu big_code = ''' 8127967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8137967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 8147967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 8157967Sgblack@eecs.umich.edu ''' 8165076Sgblack@eecs.umich.edu flag_code = ''' 8175076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8185076Sgblack@eecs.umich.edu if (shiftAmt) { 8195076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8205076Sgblack@eecs.umich.edu //worry about setting them. 8219212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8229212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8239010Snilay@cs.wisc.edu 8245076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 82511320Ssteve.reinhardt@amd.com if ((ext & (CFBit | ECFBit)) && 8266442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 8276442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 8289212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8299212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8306442Sgblack@eecs.umich.edu } 8319010Snilay@cs.wisc.edu 8325076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8335076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 8349212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 8359010Snilay@cs.wisc.edu 8365076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8379212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8389212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8399212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8409212Snilay@cs.wisc.edu 8419212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8429212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8439212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8445076Sgblack@eecs.umich.edu } 8455076Sgblack@eecs.umich.edu ''' 8465040Sgblack@eecs.umich.edu 8475076Sgblack@eecs.umich.edu class Sra(RegOp): 8487967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 8497967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 8507967Sgblack@eecs.umich.edu # them manually to be sure. 8515040Sgblack@eecs.umich.edu code = ''' 8524756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8536443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8545032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8554823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 8565040Sgblack@eecs.umich.edu ''' 8577967Sgblack@eecs.umich.edu big_code = ''' 8587967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8597967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8607967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8617967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 8627967Sgblack@eecs.umich.edu ''' 8635076Sgblack@eecs.umich.edu flag_code = ''' 8645076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8655076Sgblack@eecs.umich.edu if (shiftAmt) { 8665076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8675076Sgblack@eecs.umich.edu //worry about setting them. 8689212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8699212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8709010Snilay@cs.wisc.edu 8715076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8726444Sgblack@eecs.umich.edu uint8_t effectiveShift = 8736444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 8746444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8756444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 8769212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8779212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8786444Sgblack@eecs.umich.edu } 8799010Snilay@cs.wisc.edu 8805076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8819212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8829212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8839212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8849212Snilay@cs.wisc.edu 8859212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8869212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8879212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8885076Sgblack@eecs.umich.edu } 8895076Sgblack@eecs.umich.edu ''' 8905040Sgblack@eecs.umich.edu 8915076Sgblack@eecs.umich.edu class Ror(RegOp): 8925040Sgblack@eecs.umich.edu code = ''' 8934732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8944756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8956449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8967967Sgblack@eecs.umich.edu if (realShiftAmt) { 8976449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 8986449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 8994732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9007967Sgblack@eecs.umich.edu } else 9016447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9025040Sgblack@eecs.umich.edu ''' 9035076Sgblack@eecs.umich.edu flag_code = ''' 9045076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9055076Sgblack@eecs.umich.edu if (shiftAmt) { 9065076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9075076Sgblack@eecs.umich.edu //worry about setting them. 9089212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9099212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9109010Snilay@cs.wisc.edu 9115076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 9125076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9135076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 9145076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9159010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && msb) { 9169212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9179212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9189010Snilay@cs.wisc.edu } 9199010Snilay@cs.wisc.edu 9205076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9215076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 9229212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9239010Snilay@cs.wisc.edu 9245076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9259212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9269212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9279212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9289212Snilay@cs.wisc.edu 9299212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9309212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9319212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9325076Sgblack@eecs.umich.edu } 9335076Sgblack@eecs.umich.edu ''' 9345040Sgblack@eecs.umich.edu 9355076Sgblack@eecs.umich.edu class Rcr(RegOp): 9365040Sgblack@eecs.umich.edu code = ''' 9374733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9384756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9396454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9407967Sgblack@eecs.umich.edu if (realShiftAmt) { 9419010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9426454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 9436454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 9446454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 9456454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 9464733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9477967Sgblack@eecs.umich.edu } else 9486447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9495040Sgblack@eecs.umich.edu ''' 9505076Sgblack@eecs.umich.edu flag_code = ''' 9515076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9525076Sgblack@eecs.umich.edu if (shiftAmt) { 9539010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9545076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9555076Sgblack@eecs.umich.edu //worry about setting them. 9569212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9579212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9589010Snilay@cs.wisc.edu 9595076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9606453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 9616453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 9629212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9636453Sgblack@eecs.umich.edu } 9645076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9656454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9666454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 9676454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 9689212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9699212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9706454Sgblack@eecs.umich.edu } 9719010Snilay@cs.wisc.edu 9725076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9739212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9749212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9759212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9769212Snilay@cs.wisc.edu 9779212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9789212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9799212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9805076Sgblack@eecs.umich.edu } 9815076Sgblack@eecs.umich.edu ''' 9825040Sgblack@eecs.umich.edu 9835076Sgblack@eecs.umich.edu class Rol(RegOp): 9845040Sgblack@eecs.umich.edu code = ''' 9854732Sgblack@eecs.umich.edu uint8_t shiftAmt = 9864756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9876446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 9887967Sgblack@eecs.umich.edu if (realShiftAmt) { 9896446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9904732Sgblack@eecs.umich.edu uint64_t bottom = 9916446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 9924732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9937967Sgblack@eecs.umich.edu } else 9946447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9955040Sgblack@eecs.umich.edu ''' 9965076Sgblack@eecs.umich.edu flag_code = ''' 9975076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9985076Sgblack@eecs.umich.edu if (shiftAmt) { 9995076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10005076Sgblack@eecs.umich.edu //worry about setting them. 10019212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10029212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10039010Snilay@cs.wisc.edu 10045076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 10055076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 10065076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 10075076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10089010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && lsb) { 10099212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10109212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10119010Snilay@cs.wisc.edu } 10129010Snilay@cs.wisc.edu 10135076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10145076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 10159212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10169010Snilay@cs.wisc.edu 10175076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10189212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10199212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10209212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10219212Snilay@cs.wisc.edu 10229212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10239212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10249212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10255076Sgblack@eecs.umich.edu } 10265076Sgblack@eecs.umich.edu ''' 10275040Sgblack@eecs.umich.edu 10285076Sgblack@eecs.umich.edu class Rcl(RegOp): 10295040Sgblack@eecs.umich.edu code = ''' 10304733Sgblack@eecs.umich.edu uint8_t shiftAmt = 10314756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10326456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 10337967Sgblack@eecs.umich.edu if (realShiftAmt) { 10349010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 10356456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 10366456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 10374733Sgblack@eecs.umich.edu if(shiftAmt > 1) 10384733Sgblack@eecs.umich.edu bottom |= 10394823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 10406456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 10414733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 10427967Sgblack@eecs.umich.edu } else 10436447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 10445040Sgblack@eecs.umich.edu ''' 10455076Sgblack@eecs.umich.edu flag_code = ''' 10465076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10475076Sgblack@eecs.umich.edu if (shiftAmt) { 10489010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 10495076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10505076Sgblack@eecs.umich.edu //worry about setting them. 10519212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10529212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10539010Snilay@cs.wisc.edu 10545076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 10556456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 10565076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 105711320Ssteve.reinhardt@amd.com if ((ext & (CFBit | ECFBit)) && 10589010Snilay@cs.wisc.edu (realShiftAmt == 0) ? origCFBit : CFBits) { 10599212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10609212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10619010Snilay@cs.wisc.edu } 10629010Snilay@cs.wisc.edu 10635076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10645076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 10659212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10669010Snilay@cs.wisc.edu 10675076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10689212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10699212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10709212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10719212Snilay@cs.wisc.edu 10729212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10739212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10749212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10755076Sgblack@eecs.umich.edu } 10765076Sgblack@eecs.umich.edu ''' 10774732Sgblack@eecs.umich.edu 10786479Sgblack@eecs.umich.edu class Sld(RegOp): 10797967Sgblack@eecs.umich.edu sldCode = ''' 10806479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10816479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10827967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10836479Sgblack@eecs.umich.edu uint64_t result; 10846479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10856479Sgblack@eecs.umich.edu result = psrc1; 10866479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10876479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 10886479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 10896479Sgblack@eecs.umich.edu } else { 10906479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 10916479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 10926479Sgblack@eecs.umich.edu } 10937967Sgblack@eecs.umich.edu %s 10946479Sgblack@eecs.umich.edu ''' 10957967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 10967967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 10976479Sgblack@eecs.umich.edu flag_code = ''' 10986479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10996479Sgblack@eecs.umich.edu if (shiftAmt) { 11006479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 11016479Sgblack@eecs.umich.edu //worry about setting them. 11029212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 11039212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 11046479Sgblack@eecs.umich.edu int CFBits = 0; 11059010Snilay@cs.wisc.edu 11066479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 11076479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 11086479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 11096479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 11106479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 11116479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 11126479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 11136479Sgblack@eecs.umich.edu CFBits = 1; 11146479Sgblack@eecs.umich.edu } 11159010Snilay@cs.wisc.edu 11166479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11179010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11189212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 11199212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 11209010Snilay@cs.wisc.edu } 11219010Snilay@cs.wisc.edu 11226479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11236479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11246479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11259212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 11269010Snilay@cs.wisc.edu 11276479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11289212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 11299212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 11309212Snilay@cs.wisc.edu DestReg, psrc1, op2); 11319212Snilay@cs.wisc.edu 11329212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 11339212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 11349212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 11356479Sgblack@eecs.umich.edu } 11366479Sgblack@eecs.umich.edu ''' 11376479Sgblack@eecs.umich.edu 11386479Sgblack@eecs.umich.edu class Srd(RegOp): 11397967Sgblack@eecs.umich.edu srdCode = ''' 11406479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 11416479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 11427967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 11436479Sgblack@eecs.umich.edu uint64_t result; 11446479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 11456479Sgblack@eecs.umich.edu result = psrc1; 11466479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 11476479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 11486479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 11496479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 11506479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 11516479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 11526479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 11536479Sgblack@eecs.umich.edu } else { 11546479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 11556479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 11566479Sgblack@eecs.umich.edu logicalMask) | 11576479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 11586479Sgblack@eecs.umich.edu } 11597967Sgblack@eecs.umich.edu %s 11606479Sgblack@eecs.umich.edu ''' 11617967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 11627967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 11636479Sgblack@eecs.umich.edu flag_code = ''' 11646479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 11656479Sgblack@eecs.umich.edu if (shiftAmt) { 11666479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 11676479Sgblack@eecs.umich.edu //worry about setting them. 11689212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 11699212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 11706479Sgblack@eecs.umich.edu int CFBits = 0; 11719010Snilay@cs.wisc.edu 11726479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11736479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 11746479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 11756479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 11766479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 11776479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 11786479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 11796479Sgblack@eecs.umich.edu CFBits = 1; 11806479Sgblack@eecs.umich.edu } 11819010Snilay@cs.wisc.edu 11826479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11839010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11849212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 11859212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 11869010Snilay@cs.wisc.edu } 11879010Snilay@cs.wisc.edu 11886479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11896479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11906479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11919212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 11929010Snilay@cs.wisc.edu 11936479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11949212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 11959212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 11969212Snilay@cs.wisc.edu DestReg, psrc1, op2); 11979212Snilay@cs.wisc.edu 11989212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 11999212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 12009212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 12016479Sgblack@eecs.umich.edu } 12026479Sgblack@eecs.umich.edu ''' 12036479Sgblack@eecs.umich.edu 12046479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 12056479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 12066479Sgblack@eecs.umich.edu 12075040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 12087789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 12097789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 12105040Sgblack@eecs.umich.edu 12115040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 12129010Snilay@cs.wisc.edu code = ''' 12139010Snilay@cs.wisc.edu uint64_t newFlags = psrc1 ^ op2; 12149010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 12159010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 12169010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 12179211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 12189010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 12199010Snilay@cs.wisc.edu ''' 12205040Sgblack@eecs.umich.edu 12215426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 12225426Sgblack@eecs.umich.edu code = ''' 12235426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 12245426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 12259010Snilay@cs.wisc.edu 12265426Sgblack@eecs.umich.edu // Get only the user flags 12279010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 12289211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 12299010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 12309010Snilay@cs.wisc.edu ecfBit = 0; 12319010Snilay@cs.wisc.edu ezfBit = 0; 12329010Snilay@cs.wisc.edu 12335426Sgblack@eecs.umich.edu // Get everything else 12345426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 12355426Sgblack@eecs.umich.edu ''' 12365426Sgblack@eecs.umich.edu 12375040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 12387789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 12395040Sgblack@eecs.umich.edu 12405040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 12419211Snilay@cs.wisc.edu code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;' 12425040Sgblack@eecs.umich.edu 12435426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 12449010Snilay@cs.wisc.edu code = ''' 12459211Snilay@cs.wisc.edu DestReg = ccFlagBits | cfofBits | dfBit | 12469211Snilay@cs.wisc.edu ecfBit | ezfBit | nccFlagBits; 12479010Snilay@cs.wisc.edu ''' 12485426Sgblack@eecs.umich.edu 12495040Sgblack@eecs.umich.edu class Ruflag(RegOp): 12505040Sgblack@eecs.umich.edu code = ''' 12519211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12529211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12534951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12549010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12555040Sgblack@eecs.umich.edu ''' 12569010Snilay@cs.wisc.edu 12577967Sgblack@eecs.umich.edu big_code = ''' 12589211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12599211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12607967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12619010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12627967Sgblack@eecs.umich.edu ''' 12639010Snilay@cs.wisc.edu 12645040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12655040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12665040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 12676345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12684732Sgblack@eecs.umich.edu 12695426Sgblack@eecs.umich.edu class Rflag(RegOp): 12705426Sgblack@eecs.umich.edu code = ''' 12715426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12729211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12739010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12749010Snilay@cs.wisc.edu 12755426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12765426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12779010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12785426Sgblack@eecs.umich.edu ''' 12799010Snilay@cs.wisc.edu 12807967Sgblack@eecs.umich.edu big_code = ''' 12817967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12829211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12839010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12849010Snilay@cs.wisc.edu 12857967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12867967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12879010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12887967Sgblack@eecs.umich.edu ''' 12899010Snilay@cs.wisc.edu 12905426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12915426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12925426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 12936345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12945426Sgblack@eecs.umich.edu 12955040Sgblack@eecs.umich.edu class Sext(RegOp): 12965040Sgblack@eecs.umich.edu code = ''' 12974823Sgblack@eecs.umich.edu IntReg val = psrc1; 12985239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12995239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 13005239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 13015239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 13025007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 13035007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 13045040Sgblack@eecs.umich.edu ''' 13059010Snilay@cs.wisc.edu 13067967Sgblack@eecs.umich.edu big_code = ''' 13077967Sgblack@eecs.umich.edu IntReg val = psrc1; 13087967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 13097967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 13107967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 13117967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 13127967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 13137967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 13147967Sgblack@eecs.umich.edu ''' 13159010Snilay@cs.wisc.edu 13165239Sgblack@eecs.umich.edu flag_code = ''' 13179010Snilay@cs.wisc.edu if (!sign_bit) { 13189212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & (ZFBit)); 13199212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit)); 13209212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 13219212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 13229010Snilay@cs.wisc.edu } else { 13239212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & (ZFBit)); 13249212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit)); 13259212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 13269212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 13279010Snilay@cs.wisc.edu } 13285239Sgblack@eecs.umich.edu ''' 13294714Sgblack@eecs.umich.edu 13305040Sgblack@eecs.umich.edu class Zext(RegOp): 13315927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 13327967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 13335241Sgblack@eecs.umich.edu 13345926Sgblack@eecs.umich.edu class Rddr(RegOp): 13355926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13365926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 13376345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13387967Sgblack@eecs.umich.edu rdrCode = ''' 13395926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 13405926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 13415926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 134210474Sandreas.hansson@arm.com fault = std::make_shared<InvalidOpcode>(); 13435926Sgblack@eecs.umich.edu } else if (dr7.gd) { 134410474Sandreas.hansson@arm.com fault = std::make_shared<DebugException>(); 13455926Sgblack@eecs.umich.edu } else { 13467967Sgblack@eecs.umich.edu %s 13475926Sgblack@eecs.umich.edu } 13485926Sgblack@eecs.umich.edu ''' 13497967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 13507967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 13515926Sgblack@eecs.umich.edu 13525926Sgblack@eecs.umich.edu class Wrdr(RegOp): 13535926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13545926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 13556345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13565926Sgblack@eecs.umich.edu code = ''' 13575926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 13585926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 13595926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 136010474Sandreas.hansson@arm.com fault = std::make_shared<InvalidOpcode>(); 13616345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 13625926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 136310474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 13645926Sgblack@eecs.umich.edu } else if (dr7.gd) { 136510474Sandreas.hansson@arm.com fault = std::make_shared<DebugException>(); 13665926Sgblack@eecs.umich.edu } else { 13675926Sgblack@eecs.umich.edu DebugDest = psrc1; 13685926Sgblack@eecs.umich.edu } 13695926Sgblack@eecs.umich.edu ''' 13705926Sgblack@eecs.umich.edu 13715296Sgblack@eecs.umich.edu class Rdcr(RegOp): 13725296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13735296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 13746345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13757967Sgblack@eecs.umich.edu rdcrCode = ''' 13765924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 137710474Sandreas.hansson@arm.com fault = std::make_shared<InvalidOpcode>(); 13785296Sgblack@eecs.umich.edu } else { 13797967Sgblack@eecs.umich.edu %s 13805296Sgblack@eecs.umich.edu } 13815296Sgblack@eecs.umich.edu ''' 13827967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 13837967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 13845296Sgblack@eecs.umich.edu 13855241Sgblack@eecs.umich.edu class Wrcr(RegOp): 13865241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13875241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 13886345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13895241Sgblack@eecs.umich.edu code = ''' 13905241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 139110474Sandreas.hansson@arm.com fault = std::make_shared<InvalidOpcode>(); 13925241Sgblack@eecs.umich.edu } else { 13935241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 13945241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 13955241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 13965241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 13975241Sgblack@eecs.umich.edu 13985241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 13995241Sgblack@eecs.umich.edu switch(dest) { 14005241Sgblack@eecs.umich.edu case 0: 14015241Sgblack@eecs.umich.edu { 14025241Sgblack@eecs.umich.edu Efer efer = EferOp; 14035241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 14045241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 14055241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 14065241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 14075241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 14085241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 140910474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 14105241Sgblack@eecs.umich.edu } 14115241Sgblack@eecs.umich.edu break; 14125241Sgblack@eecs.umich.edu case 2: 14135241Sgblack@eecs.umich.edu break; 14145241Sgblack@eecs.umich.edu case 3: 14155241Sgblack@eecs.umich.edu break; 14165241Sgblack@eecs.umich.edu case 4: 14175241Sgblack@eecs.umich.edu { 14185241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 14195241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 14205241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 14215241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 142210474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 14235241Sgblack@eecs.umich.edu } 14245241Sgblack@eecs.umich.edu break; 14255241Sgblack@eecs.umich.edu case 8: 14265241Sgblack@eecs.umich.edu { 14275241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 142810474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 14295241Sgblack@eecs.umich.edu } 14305241Sgblack@eecs.umich.edu default: 143110474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 14328857Sgblack@eecs.umich.edu "Unrecognized control register %d.\\n", dest); 14335241Sgblack@eecs.umich.edu } 14345241Sgblack@eecs.umich.edu ControlDest = newVal; 14355241Sgblack@eecs.umich.edu } 14365241Sgblack@eecs.umich.edu ''' 14375290Sgblack@eecs.umich.edu 14385294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 14395672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 14405294Sgblack@eecs.umich.edu abstract = True 14415290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14425294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 14436345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14445294Sgblack@eecs.umich.edu 14455294Sgblack@eecs.umich.edu class Wrbase(SegOp): 14465290Sgblack@eecs.umich.edu code = ''' 14475294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 14485290Sgblack@eecs.umich.edu ''' 14495290Sgblack@eecs.umich.edu 14505294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 14515290Sgblack@eecs.umich.edu code = ''' 14525294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 14535294Sgblack@eecs.umich.edu ''' 14545294Sgblack@eecs.umich.edu 14555294Sgblack@eecs.umich.edu class Wrsel(SegOp): 14565294Sgblack@eecs.umich.edu code = ''' 14575294Sgblack@eecs.umich.edu SegSelDest = psrc1; 14585294Sgblack@eecs.umich.edu ''' 14595294Sgblack@eecs.umich.edu 14605905Sgblack@eecs.umich.edu class WrAttr(SegOp): 14615905Sgblack@eecs.umich.edu code = ''' 14625905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 14635905Sgblack@eecs.umich.edu ''' 14645905Sgblack@eecs.umich.edu 14655294Sgblack@eecs.umich.edu class Rdbase(SegOp): 14667967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 14677967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 14685294Sgblack@eecs.umich.edu 14695294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 14707967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 14717967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 14725294Sgblack@eecs.umich.edu 14735427Sgblack@eecs.umich.edu class RdAttr(SegOp): 14747967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 14757967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 14765427Sgblack@eecs.umich.edu 14775294Sgblack@eecs.umich.edu class Rdsel(SegOp): 14787967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 14797967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 14805294Sgblack@eecs.umich.edu 14815682Sgblack@eecs.umich.edu class Rdval(RegOp): 14825682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14836345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 14846345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14855682Sgblack@eecs.umich.edu code = ''' 14865682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 14875682Sgblack@eecs.umich.edu ''' 14885682Sgblack@eecs.umich.edu 14895682Sgblack@eecs.umich.edu class Wrval(RegOp): 14905682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14916345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 14926345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14935682Sgblack@eecs.umich.edu code = ''' 14945682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 14955682Sgblack@eecs.umich.edu ''' 14965682Sgblack@eecs.umich.edu 14975428Sgblack@eecs.umich.edu class Chks(RegOp): 14985428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 14995428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 15005428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 15015428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 15025294Sgblack@eecs.umich.edu code = ''' 15035424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 15045433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 15055433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15065433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 15075294Sgblack@eecs.umich.edu 15085428Sgblack@eecs.umich.edu switch (imm8) 15095428Sgblack@eecs.umich.edu { 15105428Sgblack@eecs.umich.edu case SegNoCheck: 15115428Sgblack@eecs.umich.edu break; 15125428Sgblack@eecs.umich.edu case SegCSCheck: 15136060Sgblack@eecs.umich.edu // Make sure it's the right type 15146060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 151510474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 15166060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 151710474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 15186060Sgblack@eecs.umich.edu } 15195428Sgblack@eecs.umich.edu break; 15205428Sgblack@eecs.umich.edu case SegCallGateCheck: 152110474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 152210474Sandreas.hansson@arm.com "CS checks for far " 15238857Sgblack@eecs.umich.edu "calls/jumps through call gates not implemented.\\n"); 15245428Sgblack@eecs.umich.edu break; 15255855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 15265853Sgblack@eecs.umich.edu // Check permissions. 15275674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 152810474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15296058Sgblack@eecs.umich.edu break; 15305674Sgblack@eecs.umich.edu } 15315855Sgblack@eecs.umich.edu // Fall through on purpose 15325855Sgblack@eecs.umich.edu case SegIntGateCheck: 15335853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 15345861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 15355853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 153610474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(0); 15375853Sgblack@eecs.umich.edu } 15385674Sgblack@eecs.umich.edu break; 15395428Sgblack@eecs.umich.edu case SegSSCheck: 15405433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 15415433Sgblack@eecs.umich.edu if (!desc.p) { 154210474Sandreas.hansson@arm.com fault = std::make_shared<StackFault>(selector); 15438626Sgblack@eecs.umich.edu } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 15448626Sgblack@eecs.umich.edu desc.type.w) || 15455433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 15465433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 154710474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15485433Sgblack@eecs.umich.edu } 15498626Sgblack@eecs.umich.edu } else if (m5reg.submode != SixtyFourBitMode || 15508626Sgblack@eecs.umich.edu m5reg.cpl == 3) { 155110474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15525433Sgblack@eecs.umich.edu } 15535428Sgblack@eecs.umich.edu break; 15545428Sgblack@eecs.umich.edu case SegIretCheck: 15555428Sgblack@eecs.umich.edu { 15565433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 15575433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 15585433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 15595433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 15605679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 156110474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15625679Sgblack@eecs.umich.edu } else if (!desc.p) { 156310474Sandreas.hansson@arm.com fault = std::make_shared<SegmentNotPresent>(selector); 15645679Sgblack@eecs.umich.edu } 15655428Sgblack@eecs.umich.edu break; 15665428Sgblack@eecs.umich.edu } 15675428Sgblack@eecs.umich.edu case SegIntCSCheck: 15685675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 15695675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 157010474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15715675Sgblack@eecs.umich.edu } 15725675Sgblack@eecs.umich.edu } else { 157310474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 157410474Sandreas.hansson@arm.com "Interrupt CS " 15758857Sgblack@eecs.umich.edu "checks not implemented in legacy mode.\\n"); 15765675Sgblack@eecs.umich.edu } 15775428Sgblack@eecs.umich.edu break; 15785899Sgblack@eecs.umich.edu case SegTRCheck: 15795899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 158010474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15815899Sgblack@eecs.umich.edu } 15825899Sgblack@eecs.umich.edu break; 15835900Sgblack@eecs.umich.edu case SegTSSCheck: 15845900Sgblack@eecs.umich.edu if (!desc.p) { 158510474Sandreas.hansson@arm.com fault = std::make_shared<SegmentNotPresent>(selector); 15865900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 15875900Sgblack@eecs.umich.edu (desc.type == 1 && 15885900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 158910474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15905900Sgblack@eecs.umich.edu } 15915900Sgblack@eecs.umich.edu break; 15925936Sgblack@eecs.umich.edu case SegInGDTCheck: 15935936Sgblack@eecs.umich.edu if (selector.ti) { 159410474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 15955936Sgblack@eecs.umich.edu } 15965936Sgblack@eecs.umich.edu break; 15975936Sgblack@eecs.umich.edu case SegLDTCheck: 15985936Sgblack@eecs.umich.edu if (!desc.p) { 159910474Sandreas.hansson@arm.com fault = std::make_shared<SegmentNotPresent>(selector); 16005936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 160110474Sandreas.hansson@arm.com fault = std::make_shared<GeneralProtection>(selector); 16025936Sgblack@eecs.umich.edu } 16035936Sgblack@eecs.umich.edu break; 16045428Sgblack@eecs.umich.edu default: 160510474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 16068857Sgblack@eecs.umich.edu "Undefined segment check type.\\n"); 16075428Sgblack@eecs.umich.edu } 16085294Sgblack@eecs.umich.edu ''' 16095294Sgblack@eecs.umich.edu flag_code = ''' 16105294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 16119212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & ZFBit); 16129212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 16139010Snilay@cs.wisc.edu 16149010Snilay@cs.wisc.edu if (!selector.si && !selector.ti) { 16159212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & ZFBit); 16169212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 16179010Snilay@cs.wisc.edu } 16185294Sgblack@eecs.umich.edu ''' 16195294Sgblack@eecs.umich.edu 16205294Sgblack@eecs.umich.edu class Wrdh(RegOp): 16215294Sgblack@eecs.umich.edu code = ''' 16225678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 16235294Sgblack@eecs.umich.edu 16245678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 16255678Sgblack@eecs.umich.edu switch(desc.type) { 16265678Sgblack@eecs.umich.edu case LDT64: 16275678Sgblack@eecs.umich.edu case AvailableTSS64: 16285678Sgblack@eecs.umich.edu case BusyTSS64: 16295678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 16305678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 16315678Sgblack@eecs.umich.edu break; 16325678Sgblack@eecs.umich.edu case CallGate64: 16335678Sgblack@eecs.umich.edu case IntGate64: 16345678Sgblack@eecs.umich.edu case TrapGate64: 16355678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 16365678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 16375678Sgblack@eecs.umich.edu break; 16385678Sgblack@eecs.umich.edu default: 163910474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 16408857Sgblack@eecs.umich.edu "Wrdh used with wrong descriptor type!\\n"); 16415678Sgblack@eecs.umich.edu } 16425678Sgblack@eecs.umich.edu DestReg = target; 16435294Sgblack@eecs.umich.edu ''' 16445294Sgblack@eecs.umich.edu 16455409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 16465409Sgblack@eecs.umich.edu code = ''' 16475409Sgblack@eecs.umich.edu TscOp = psrc1; 16485409Sgblack@eecs.umich.edu ''' 16495409Sgblack@eecs.umich.edu 16505409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 16515409Sgblack@eecs.umich.edu code = ''' 16525409Sgblack@eecs.umich.edu DestReg = TscOp; 16535409Sgblack@eecs.umich.edu ''' 16545409Sgblack@eecs.umich.edu 16555429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 16565429Sgblack@eecs.umich.edu code = ''' 16575429Sgblack@eecs.umich.edu DestReg = M5Reg; 16585429Sgblack@eecs.umich.edu ''' 16595429Sgblack@eecs.umich.edu 16605294Sgblack@eecs.umich.edu class Wrdl(RegOp): 16615294Sgblack@eecs.umich.edu code = ''' 16625294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 16635433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 16648857Sgblack@eecs.umich.edu // This while loop is so we can use break statements in the code 16658857Sgblack@eecs.umich.edu // below to skip the rest of this section without a bunch of 16668857Sgblack@eecs.umich.edu // nesting. 16678857Sgblack@eecs.umich.edu while (true) { 16688857Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 16698857Sgblack@eecs.umich.edu if (!desc.p) { 167010474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 16718857Sgblack@eecs.umich.edu "Segment not present.\\n"); 16728857Sgblack@eecs.umich.edu break; 16735901Sgblack@eecs.umich.edu } 16748857Sgblack@eecs.umich.edu SegAttr attr = 0; 16758857Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 16768857Sgblack@eecs.umich.edu attr.unusable = 0; 16778857Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 16788857Sgblack@eecs.umich.edu attr.longMode = desc.l; 16798857Sgblack@eecs.umich.edu attr.avl = desc.avl; 16808857Sgblack@eecs.umich.edu attr.granularity = desc.g; 16818857Sgblack@eecs.umich.edu attr.present = desc.p; 16828857Sgblack@eecs.umich.edu attr.system = desc.s; 16838857Sgblack@eecs.umich.edu attr.type = desc.type; 16848857Sgblack@eecs.umich.edu if (!desc.s) { 16858857Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 16868857Sgblack@eecs.umich.edu if (desc.type.e) { 168710474Sandreas.hansson@arm.com fault = std::make_shared<GenericISA::M5PanicFault>( 16888857Sgblack@eecs.umich.edu "Gate descriptor encountered.\\n"); 16898857Sgblack@eecs.umich.edu break; 16908857Sgblack@eecs.umich.edu } 16918857Sgblack@eecs.umich.edu attr.readable = 1; 16928857Sgblack@eecs.umich.edu attr.writable = 1; 16938857Sgblack@eecs.umich.edu attr.expandDown = 0; 16948857Sgblack@eecs.umich.edu } else { 16958857Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 16968857Sgblack@eecs.umich.edu attr.expandDown = 0; 16978857Sgblack@eecs.umich.edu attr.readable = desc.type.r; 16988857Sgblack@eecs.umich.edu attr.writable = 0; 16998857Sgblack@eecs.umich.edu } else { 17008857Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 17018857Sgblack@eecs.umich.edu attr.readable = 1; 17028857Sgblack@eecs.umich.edu attr.writable = desc.type.w; 17038857Sgblack@eecs.umich.edu } 17048857Sgblack@eecs.umich.edu } 17058857Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 17068857Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 17078857Sgblack@eecs.umich.edu if (desc.g) 17088857Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 17098857Sgblack@eecs.umich.edu SegBaseDest = base; 17108857Sgblack@eecs.umich.edu SegLimitDest = limit; 17118857Sgblack@eecs.umich.edu SegAttrDest = attr; 17125433Sgblack@eecs.umich.edu } else { 17138857Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 17148857Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 17158857Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 17165433Sgblack@eecs.umich.edu } 17178857Sgblack@eecs.umich.edu break; 17185294Sgblack@eecs.umich.edu } 17195290Sgblack@eecs.umich.edu ''' 17209896Sandreas@sandberg.pp.se 17219896Sandreas@sandberg.pp.se class Wrxftw(WrRegOp): 17229896Sandreas@sandberg.pp.se def __init__(self, src1, **kwargs): 17239896Sandreas@sandberg.pp.se super(Wrxftw, self).__init__(src1, "InstRegIndex(NUM_INTREGS)", \ 17249896Sandreas@sandberg.pp.se **kwargs) 17259896Sandreas@sandberg.pp.se 17269896Sandreas@sandberg.pp.se code = ''' 17279896Sandreas@sandberg.pp.se FTW = X86ISA::convX87XTagsToTags(SrcReg1); 17289896Sandreas@sandberg.pp.se ''' 17299896Sandreas@sandberg.pp.se 17309896Sandreas@sandberg.pp.se class Rdxftw(RdRegOp): 17319896Sandreas@sandberg.pp.se code = ''' 17329896Sandreas@sandberg.pp.se DestReg = X86ISA::convX87TagsToXTags(FTW); 17339896Sandreas@sandberg.pp.se ''' 17344519Sgblack@eecs.umich.edu}}; 1735