regop.isa revision 10196
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 124519Sgblack@eecs.umich.edu// 137087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 147087Snate@binkert.org// modification, are permitted provided that the following conditions are 157087Snate@binkert.org// met: redistributions of source code must retain the above copyright 167087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org// documentation and/or other materials provided with the distribution; 207087Snate@binkert.org// neither the name of the copyright holders nor the names of its 214519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 227087Snate@binkert.org// this software without specific prior written permission. 234519Sgblack@eecs.umich.edu// 244519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354519Sgblack@eecs.umich.edu// 364519Sgblack@eecs.umich.edu// Authors: Gabe Black 374519Sgblack@eecs.umich.edu 384519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 394519Sgblack@eecs.umich.edu// 404519Sgblack@eecs.umich.edu// RegOp Microop templates 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434519Sgblack@eecs.umich.edu 444519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 4510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 464519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 474519Sgblack@eecs.umich.edu { 484519Sgblack@eecs.umich.edu Fault fault = NoFault; 494519Sgblack@eecs.umich.edu 504809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 514519Sgblack@eecs.umich.edu %(op_decl)s; 524519Sgblack@eecs.umich.edu %(op_rd)s; 534688Sgblack@eecs.umich.edu 547969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 557969Sgblack@eecs.umich.edu 564688Sgblack@eecs.umich.edu if(%(cond_check)s) 574688Sgblack@eecs.umich.edu { 584688Sgblack@eecs.umich.edu %(code)s; 594688Sgblack@eecs.umich.edu %(flag_code)s; 604688Sgblack@eecs.umich.edu } 614708Sgblack@eecs.umich.edu else 624708Sgblack@eecs.umich.edu { 634708Sgblack@eecs.umich.edu %(else_code)s; 644708Sgblack@eecs.umich.edu } 654519Sgblack@eecs.umich.edu 664519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 674519Sgblack@eecs.umich.edu if(fault == NoFault) 684519Sgblack@eecs.umich.edu { 694519Sgblack@eecs.umich.edu %(op_wb)s; 704519Sgblack@eecs.umich.edu } 714519Sgblack@eecs.umich.edu return fault; 724519Sgblack@eecs.umich.edu } 734519Sgblack@eecs.umich.edu}}; 744519Sgblack@eecs.umich.edu 754519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 7610196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 774519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 784519Sgblack@eecs.umich.edu { 794519Sgblack@eecs.umich.edu Fault fault = NoFault; 804519Sgblack@eecs.umich.edu 814519Sgblack@eecs.umich.edu %(op_decl)s; 824519Sgblack@eecs.umich.edu %(op_rd)s; 834688Sgblack@eecs.umich.edu 847969Sgblack@eecs.umich.edu IntReg result M5_VAR_USED; 857969Sgblack@eecs.umich.edu 864688Sgblack@eecs.umich.edu if(%(cond_check)s) 874688Sgblack@eecs.umich.edu { 884688Sgblack@eecs.umich.edu %(code)s; 894688Sgblack@eecs.umich.edu %(flag_code)s; 904688Sgblack@eecs.umich.edu } 914708Sgblack@eecs.umich.edu else 924708Sgblack@eecs.umich.edu { 934708Sgblack@eecs.umich.edu %(else_code)s; 944708Sgblack@eecs.umich.edu } 954519Sgblack@eecs.umich.edu 964519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 974519Sgblack@eecs.umich.edu if(fault == NoFault) 984519Sgblack@eecs.umich.edu { 994519Sgblack@eecs.umich.edu %(op_wb)s; 1004519Sgblack@eecs.umich.edu } 1014519Sgblack@eecs.umich.edu return fault; 1024519Sgblack@eecs.umich.edu } 1034519Sgblack@eecs.umich.edu}}; 1044519Sgblack@eecs.umich.edu 1054519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1064519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1074519Sgblack@eecs.umich.edu { 1084519Sgblack@eecs.umich.edu public: 1094519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1107620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1116345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1124712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1134519Sgblack@eecs.umich.edu 1144519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1154519Sgblack@eecs.umich.edu }; 1164519Sgblack@eecs.umich.edu}}; 1174519Sgblack@eecs.umich.edu 1184519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1194519Sgblack@eecs.umich.edu 1204951Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu public: 1234951Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1247620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 1256646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1264712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1274519Sgblack@eecs.umich.edu 1284519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1294519Sgblack@eecs.umich.edu }; 1304519Sgblack@eecs.umich.edu}}; 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 13310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s( 1347620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1356345Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1364712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1377620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1384688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1394581Sgblack@eecs.umich.edu %(op_class)s) 1404519Sgblack@eecs.umich.edu { 1417626Sgblack@eecs.umich.edu %(constructor)s; 1427894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1434519Sgblack@eecs.umich.edu } 1444519Sgblack@eecs.umich.edu}}; 1454519Sgblack@eecs.umich.edu 1464519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 14710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s( 1487620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 1496646Sgblack@eecs.umich.edu InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1504712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1517620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 1524688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 1534581Sgblack@eecs.umich.edu %(op_class)s) 1544519Sgblack@eecs.umich.edu { 1557626Sgblack@eecs.umich.edu %(constructor)s; 1567894SBrad.Beckmann@amd.com %(cond_control_flag_init)s; 1574519Sgblack@eecs.umich.edu } 1584519Sgblack@eecs.umich.edu}}; 1594519Sgblack@eecs.umich.edu 1605075Sgblack@eecs.umich.eduoutput header {{ 1615075Sgblack@eecs.umich.edu void 1625075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1635075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 1645428Sgblack@eecs.umich.edu 1655428Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 1665674Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 1675899Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 1685936Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 1695428Sgblack@eecs.umich.edu }; 1705678Sgblack@eecs.umich.edu 1715678Sgblack@eecs.umich.edu enum LongModeDescriptorType { 1725678Sgblack@eecs.umich.edu LDT64 = 2, 1735678Sgblack@eecs.umich.edu AvailableTSS64 = 9, 1745678Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 1755678Sgblack@eecs.umich.edu CallGate64 = 0xc, 1765678Sgblack@eecs.umich.edu IntGate64 = 0xe, 1775678Sgblack@eecs.umich.edu TrapGate64 = 0xf 1785678Sgblack@eecs.umich.edu }; 1795075Sgblack@eecs.umich.edu}}; 1805075Sgblack@eecs.umich.edu 1815075Sgblack@eecs.umich.eduoutput decoder {{ 1825075Sgblack@eecs.umich.edu void 1835075Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 1845075Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 1855075Sgblack@eecs.umich.edu { 1865075Sgblack@eecs.umich.edu //Check for divide by zero. 1877719Sgblack@eecs.umich.edu assert(divisor != 0); 1885075Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 1895075Sgblack@eecs.umich.edu if (divisor <= dividend) { 1905075Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 1915075Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 1925075Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 1935075Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 1945075Sgblack@eecs.umich.edu divisor <<= shift; 1955075Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 1965075Sgblack@eecs.umich.edu //now larger than the dividend. 1975075Sgblack@eecs.umich.edu uint64_t quotientBit = 1; 1985075Sgblack@eecs.umich.edu quotientBit <<= shift; 1995075Sgblack@eecs.umich.edu //If we need to step back a bit (no pun intended) because the 2005075Sgblack@eecs.umich.edu //divisor got too to large, do that here. This is the "or two" 2015075Sgblack@eecs.umich.edu //part of one or two bit division. 2025075Sgblack@eecs.umich.edu if (divisor > dividend) { 2035075Sgblack@eecs.umich.edu quotientBit >>= 1; 2045075Sgblack@eecs.umich.edu divisor >>= 1; 2055075Sgblack@eecs.umich.edu } 2065075Sgblack@eecs.umich.edu //Decrement the remainder and increment the quotient. 2075075Sgblack@eecs.umich.edu quotient += quotientBit; 2085075Sgblack@eecs.umich.edu remainder -= divisor; 2095075Sgblack@eecs.umich.edu } 2105075Sgblack@eecs.umich.edu } 2115075Sgblack@eecs.umich.edu}}; 2125075Sgblack@eecs.umich.edu 2134519Sgblack@eecs.umich.edulet {{ 2145040Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 2155040Sgblack@eecs.umich.edu # them will always work. 2165040Sgblack@eecs.umich.edu header_output = "" 2175040Sgblack@eecs.umich.edu decoder_output = "" 2185040Sgblack@eecs.umich.edu exec_output = "" 2195040Sgblack@eecs.umich.edu 2205040Sgblack@eecs.umich.edu immTemplates = ( 2215040Sgblack@eecs.umich.edu MicroRegOpImmDeclare, 2225040Sgblack@eecs.umich.edu MicroRegOpImmConstructor, 2235040Sgblack@eecs.umich.edu MicroRegOpImmExecute) 2245040Sgblack@eecs.umich.edu 2255040Sgblack@eecs.umich.edu regTemplates = ( 2265040Sgblack@eecs.umich.edu MicroRegOpDeclare, 2275040Sgblack@eecs.umich.edu MicroRegOpConstructor, 2285040Sgblack@eecs.umich.edu MicroRegOpExecute) 2295040Sgblack@eecs.umich.edu 2305040Sgblack@eecs.umich.edu class RegOpMeta(type): 2317967Sgblack@eecs.umich.edu def buildCppClasses(self, name, Name, suffix, code, big_code, \ 2329699Snilay@cs.wisc.edu flag_code, cond_check, else_code, cond_control_flag_init, 2339699Snilay@cs.wisc.edu op_class): 2345040Sgblack@eecs.umich.edu 2355040Sgblack@eecs.umich.edu # Globals to stick the output in 2365040Sgblack@eecs.umich.edu global header_output 2375040Sgblack@eecs.umich.edu global decoder_output 2385040Sgblack@eecs.umich.edu global exec_output 2395040Sgblack@eecs.umich.edu 2405040Sgblack@eecs.umich.edu # Stick all the code together so it can be searched at once 2417894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 2427894SBrad.Beckmann@amd.com cond_control_flag_init)) 2437967Sgblack@eecs.umich.edu allBigCode = "|".join((big_code, flag_code, cond_check, else_code, 2447967Sgblack@eecs.umich.edu cond_control_flag_init)) 2455040Sgblack@eecs.umich.edu 2465040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 2475040Sgblack@eecs.umich.edu # of this code. 2488588Sgblack@eecs.umich.edu matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?") 2497967Sgblack@eecs.umich.edu match = matcher.search(allCode + allBigCode) 2505062Sgblack@eecs.umich.edu if match: 2515062Sgblack@eecs.umich.edu typeQual = "" 2525062Sgblack@eecs.umich.edu if match.group("typeQual"): 2535062Sgblack@eecs.umich.edu typeQual = match.group("typeQual") 2545062Sgblack@eecs.umich.edu src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 2555040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2565062Sgblack@eecs.umich.edu matcher.sub(src2_name, code), 2577967Sgblack@eecs.umich.edu matcher.sub(src2_name, big_code), 2585062Sgblack@eecs.umich.edu matcher.sub(src2_name, flag_code), 2595062Sgblack@eecs.umich.edu matcher.sub(src2_name, cond_check), 2607894SBrad.Beckmann@amd.com matcher.sub(src2_name, else_code), 2619699Snilay@cs.wisc.edu matcher.sub(src2_name, cond_control_flag_init), 2629699Snilay@cs.wisc.edu op_class) 2636647Sgblack@eecs.umich.edu imm_name = "%simm8" % match.group("prefix") 2645040Sgblack@eecs.umich.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 2656647Sgblack@eecs.umich.edu matcher.sub(imm_name, code), 2667967Sgblack@eecs.umich.edu matcher.sub(imm_name, big_code), 2676647Sgblack@eecs.umich.edu matcher.sub(imm_name, flag_code), 2686647Sgblack@eecs.umich.edu matcher.sub(imm_name, cond_check), 2697894SBrad.Beckmann@amd.com matcher.sub(imm_name, else_code), 2709699Snilay@cs.wisc.edu matcher.sub(imm_name, cond_control_flag_init), 2719699Snilay@cs.wisc.edu op_class) 2725040Sgblack@eecs.umich.edu return 2735040Sgblack@eecs.umich.edu 2745040Sgblack@eecs.umich.edu # If there's something optional to do with flags, generate 2755040Sgblack@eecs.umich.edu # a version without it and fix up this version to use it. 2765239Sgblack@eecs.umich.edu if flag_code != "" or cond_check != "true": 2775040Sgblack@eecs.umich.edu self.buildCppClasses(name, Name, suffix, 2789699Snilay@cs.wisc.edu code, big_code, "", "true", else_code, "", op_class) 2795040Sgblack@eecs.umich.edu suffix = "Flags" + suffix 2805040Sgblack@eecs.umich.edu 2815040Sgblack@eecs.umich.edu # If psrc1 or psrc2 is used, we need to actually insert code to 2825040Sgblack@eecs.umich.edu # compute it. 2837967Sgblack@eecs.umich.edu for (big, all) in ((False, allCode), (True, allBigCode)): 2847967Sgblack@eecs.umich.edu prefix = "" 2857967Sgblack@eecs.umich.edu for (rex, decl) in ( 2867967Sgblack@eecs.umich.edu ("(?<!\w)psrc1(?!\w)", 2877967Sgblack@eecs.umich.edu "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), 2887967Sgblack@eecs.umich.edu ("(?<!\w)psrc2(?!\w)", 2897967Sgblack@eecs.umich.edu "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), 2907967Sgblack@eecs.umich.edu ("(?<!\w)spsrc1(?!\w)", 2917967Sgblack@eecs.umich.edu "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), 2927967Sgblack@eecs.umich.edu ("(?<!\w)spsrc2(?!\w)", 2937967Sgblack@eecs.umich.edu "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), 2947967Sgblack@eecs.umich.edu ("(?<!\w)simm8(?!\w)", 2957967Sgblack@eecs.umich.edu "int8_t simm8 = imm8;")): 2967967Sgblack@eecs.umich.edu matcher = re.compile(rex) 2977967Sgblack@eecs.umich.edu if matcher.search(all): 2987967Sgblack@eecs.umich.edu prefix += decl + "\n" 2997967Sgblack@eecs.umich.edu if big: 3007967Sgblack@eecs.umich.edu if big_code != "": 3017967Sgblack@eecs.umich.edu big_code = prefix + big_code 3027967Sgblack@eecs.umich.edu else: 3037967Sgblack@eecs.umich.edu code = prefix + code 3045040Sgblack@eecs.umich.edu 3055040Sgblack@eecs.umich.edu base = "X86ISA::RegOp" 3065040Sgblack@eecs.umich.edu 3075040Sgblack@eecs.umich.edu # If imm8 shows up in the code, use the immediate templates, if 3085040Sgblack@eecs.umich.edu # not, hopefully the register ones will be correct. 3095040Sgblack@eecs.umich.edu templates = regTemplates 3106647Sgblack@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3115040Sgblack@eecs.umich.edu if matcher.search(allCode): 3125040Sgblack@eecs.umich.edu base += "Imm" 3135040Sgblack@eecs.umich.edu templates = immTemplates 3145040Sgblack@eecs.umich.edu 3155040Sgblack@eecs.umich.edu # Get everything ready for the substitution 3167967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name + suffix, base, 3175040Sgblack@eecs.umich.edu {"code" : code, 3185040Sgblack@eecs.umich.edu "flag_code" : flag_code, 3195040Sgblack@eecs.umich.edu "cond_check" : cond_check, 3207894SBrad.Beckmann@amd.com "else_code" : else_code, 3219699Snilay@cs.wisc.edu "cond_control_flag_init" : cond_control_flag_init, 3229699Snilay@cs.wisc.edu "op_class" : op_class})] 3237967Sgblack@eecs.umich.edu if big_code != "": 3247967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + suffix + "Big", base, 3257967Sgblack@eecs.umich.edu {"code" : big_code, 3267967Sgblack@eecs.umich.edu "flag_code" : flag_code, 3277967Sgblack@eecs.umich.edu "cond_check" : cond_check, 3287967Sgblack@eecs.umich.edu "else_code" : else_code, 3299699Snilay@cs.wisc.edu "cond_control_flag_init" : cond_control_flag_init, 3309699Snilay@cs.wisc.edu "op_class" : op_class})] 3315040Sgblack@eecs.umich.edu 3325040Sgblack@eecs.umich.edu # Generate the actual code (finally!) 3337967Sgblack@eecs.umich.edu for iop in iops: 3347967Sgblack@eecs.umich.edu header_output += templates[0].subst(iop) 3357967Sgblack@eecs.umich.edu decoder_output += templates[1].subst(iop) 3367967Sgblack@eecs.umich.edu exec_output += templates[2].subst(iop) 3375040Sgblack@eecs.umich.edu 3385040Sgblack@eecs.umich.edu 3395040Sgblack@eecs.umich.edu def __new__(mcls, Name, bases, dict): 3404688Sgblack@eecs.umich.edu abstract = False 3415040Sgblack@eecs.umich.edu name = Name.lower() 3424688Sgblack@eecs.umich.edu if "abstract" in dict: 3434688Sgblack@eecs.umich.edu abstract = dict['abstract'] 3444688Sgblack@eecs.umich.edu del dict['abstract'] 3454688Sgblack@eecs.umich.edu 3465040Sgblack@eecs.umich.edu cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3474688Sgblack@eecs.umich.edu if not abstract: 3485040Sgblack@eecs.umich.edu cls.className = Name 3495040Sgblack@eecs.umich.edu cls.base_mnemonic = name 3505040Sgblack@eecs.umich.edu code = cls.code 3517967Sgblack@eecs.umich.edu big_code = cls.big_code 3525040Sgblack@eecs.umich.edu flag_code = cls.flag_code 3535040Sgblack@eecs.umich.edu cond_check = cls.cond_check 3545040Sgblack@eecs.umich.edu else_code = cls.else_code 3557894SBrad.Beckmann@amd.com cond_control_flag_init = cls.cond_control_flag_init 3569699Snilay@cs.wisc.edu op_class = cls.op_class 3575040Sgblack@eecs.umich.edu 3585040Sgblack@eecs.umich.edu # Set up the C++ classes 3597967Sgblack@eecs.umich.edu mcls.buildCppClasses(cls, name, Name, "", code, big_code, 3607967Sgblack@eecs.umich.edu flag_code, cond_check, else_code, 3619699Snilay@cs.wisc.edu cond_control_flag_init, op_class) 3625040Sgblack@eecs.umich.edu 3635040Sgblack@eecs.umich.edu # Hook into the microassembler dict 3645040Sgblack@eecs.umich.edu global microopClasses 3655040Sgblack@eecs.umich.edu microopClasses[name] = cls 3665040Sgblack@eecs.umich.edu 3677894SBrad.Beckmann@amd.com allCode = "|".join((code, flag_code, cond_check, else_code, 3687894SBrad.Beckmann@amd.com cond_control_flag_init)) 3695040Sgblack@eecs.umich.edu 3705040Sgblack@eecs.umich.edu # If op2 is used anywhere, make register and immediate versions 3715040Sgblack@eecs.umich.edu # of this code. 3728588Sgblack@eecs.umich.edu matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?") 3735040Sgblack@eecs.umich.edu if matcher.search(allCode): 3745040Sgblack@eecs.umich.edu microopClasses[name + 'i'] = cls 3754688Sgblack@eecs.umich.edu return cls 3764688Sgblack@eecs.umich.edu 3775040Sgblack@eecs.umich.edu 3785040Sgblack@eecs.umich.edu class RegOp(X86Microop): 3795040Sgblack@eecs.umich.edu __metaclass__ = RegOpMeta 3805040Sgblack@eecs.umich.edu # This class itself doesn't act as a microop 3814688Sgblack@eecs.umich.edu abstract = True 3824688Sgblack@eecs.umich.edu 3835040Sgblack@eecs.umich.edu # Default template parameter values 3847967Sgblack@eecs.umich.edu big_code = "" 3855040Sgblack@eecs.umich.edu flag_code = "" 3865040Sgblack@eecs.umich.edu cond_check = "true" 3875040Sgblack@eecs.umich.edu else_code = ";" 3887894SBrad.Beckmann@amd.com cond_control_flag_init = "" 3899699Snilay@cs.wisc.edu op_class = "IntAluOp" 3905040Sgblack@eecs.umich.edu 3915040Sgblack@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 3924519Sgblack@eecs.umich.edu self.dest = dest 3934519Sgblack@eecs.umich.edu self.src1 = src1 3945040Sgblack@eecs.umich.edu self.op2 = op2 3954688Sgblack@eecs.umich.edu self.flags = flags 3964701Sgblack@eecs.umich.edu self.dataSize = dataSize 3974688Sgblack@eecs.umich.edu if flags is None: 3984688Sgblack@eecs.umich.edu self.ext = 0 3994688Sgblack@eecs.umich.edu else: 4004688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4014688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4024688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 4034688Sgblack@eecs.umich.edu self.className += "Flags" 4044519Sgblack@eecs.umich.edu 4057620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 4067967Sgblack@eecs.umich.edu if self.big_code != "": 4077967Sgblack@eecs.umich.edu className = self.className 4087967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4097967Sgblack@eecs.umich.edu className += "Imm" 4107967Sgblack@eecs.umich.edu allocString = ''' 4117967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 4127967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 4137967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4147967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) : 4157967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 4167967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, 4177967Sgblack@eecs.umich.edu %(dest)s, %(dataSize)s, %(ext)s)) 4187967Sgblack@eecs.umich.edu ''' 4197967Sgblack@eecs.umich.edu allocator = allocString % { 4207967Sgblack@eecs.umich.edu "class_name" : className, 4217967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4227967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4237967Sgblack@eecs.umich.edu "dest" : self.dest, 4247967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4257967Sgblack@eecs.umich.edu "ext" : self.ext} 4267967Sgblack@eecs.umich.edu return allocator 4277967Sgblack@eecs.umich.edu else: 4287967Sgblack@eecs.umich.edu className = self.className 4297967Sgblack@eecs.umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4307967Sgblack@eecs.umich.edu className += "Imm" 4317967Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 4327967Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4337967Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4347967Sgblack@eecs.umich.edu "class_name" : className, 4357967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4367967Sgblack@eecs.umich.edu "src1" : self.src1, "op2" : self.op2, 4377967Sgblack@eecs.umich.edu "dest" : self.dest, 4387967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 4397967Sgblack@eecs.umich.edu "ext" : self.ext} 4407967Sgblack@eecs.umich.edu return allocator 4414519Sgblack@eecs.umich.edu 4425040Sgblack@eecs.umich.edu class LogicRegOp(RegOp): 4434688Sgblack@eecs.umich.edu abstract = True 4445040Sgblack@eecs.umich.edu flag_code = ''' 4455040Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 4465115Sgblack@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4479212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 4489212Snilay@cs.wisc.edu PredezfBit, ext & ~mask, result, psrc1, op2); 4499212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4509212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4519212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4529010Snilay@cs.wisc.edu 4535040Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4549212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~((CFBit | OFBit) & ext); 4559212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ECFBit & ext); 4565040Sgblack@eecs.umich.edu ''' 4574519Sgblack@eecs.umich.edu 4585040Sgblack@eecs.umich.edu class FlagRegOp(RegOp): 4595040Sgblack@eecs.umich.edu abstract = True 4609010Snilay@cs.wisc.edu flag_code = ''' 4619212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4629212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4639212Snilay@cs.wisc.edu ext, result, psrc1, op2); 4649212Snilay@cs.wisc.edu 4659212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4669212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4679212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4689212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4699212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4709010Snilay@cs.wisc.edu ''' 4714519Sgblack@eecs.umich.edu 4725040Sgblack@eecs.umich.edu class SubRegOp(RegOp): 4735040Sgblack@eecs.umich.edu abstract = True 4749010Snilay@cs.wisc.edu flag_code = ''' 4759212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PredcfofBits | 4769212Snilay@cs.wisc.edu PreddfBit | PredecfBit | PredezfBit, 4779212Snilay@cs.wisc.edu ext, result, psrc1, ~op2, true); 4789212Snilay@cs.wisc.edu 4799212Snilay@cs.wisc.edu PredcfofBits = newFlags & cfofMask; 4809212Snilay@cs.wisc.edu PredecfBit = newFlags & ECFBit; 4819212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 4829212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 4839212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 4849010Snilay@cs.wisc.edu ''' 4854519Sgblack@eecs.umich.edu 4865040Sgblack@eecs.umich.edu class CondRegOp(RegOp): 4875040Sgblack@eecs.umich.edu abstract = True 4889211Snilay@cs.wisc.edu cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | ecfBit | \ 4899211Snilay@cs.wisc.edu ezfBit, ext)" 4907894SBrad.Beckmann@amd.com cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" 4914519Sgblack@eecs.umich.edu 4925063Sgblack@eecs.umich.edu class RdRegOp(RegOp): 4935063Sgblack@eecs.umich.edu abstract = True 4945063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4955063Sgblack@eecs.umich.edu if not src1: 4965063Sgblack@eecs.umich.edu src1 = dest 4976345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 4986345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", None, dataSize) 4995063Sgblack@eecs.umich.edu 5005063Sgblack@eecs.umich.edu class WrRegOp(RegOp): 5015063Sgblack@eecs.umich.edu abstract = True 5025063Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 5036345Sgblack@eecs.umich.edu super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 5046345Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 5055063Sgblack@eecs.umich.edu 5065040Sgblack@eecs.umich.edu class Add(FlagRegOp): 5077969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' 5087969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' 5094595Sgblack@eecs.umich.edu 5105040Sgblack@eecs.umich.edu class Or(LogicRegOp): 5117969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' 5127969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' 5134595Sgblack@eecs.umich.edu 5145040Sgblack@eecs.umich.edu class Adc(FlagRegOp): 5155040Sgblack@eecs.umich.edu code = ''' 5169010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5177969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); 5185040Sgblack@eecs.umich.edu ''' 5197967Sgblack@eecs.umich.edu big_code = ''' 5209010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5217969Sgblack@eecs.umich.edu DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); 5227967Sgblack@eecs.umich.edu ''' 5235040Sgblack@eecs.umich.edu 5245040Sgblack@eecs.umich.edu class Sbb(SubRegOp): 5255040Sgblack@eecs.umich.edu code = ''' 5269010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5277969Sgblack@eecs.umich.edu DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); 5285040Sgblack@eecs.umich.edu ''' 5297967Sgblack@eecs.umich.edu big_code = ''' 5309010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 5317969Sgblack@eecs.umich.edu DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); 5327967Sgblack@eecs.umich.edu ''' 5335040Sgblack@eecs.umich.edu 5345040Sgblack@eecs.umich.edu class And(LogicRegOp): 5357969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' 5367969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' 5375040Sgblack@eecs.umich.edu 5385040Sgblack@eecs.umich.edu class Sub(SubRegOp): 5397969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' 5407969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' 5415040Sgblack@eecs.umich.edu 5425040Sgblack@eecs.umich.edu class Xor(LogicRegOp): 5437969Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' 5447969Sgblack@eecs.umich.edu big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' 5455040Sgblack@eecs.umich.edu 5465063Sgblack@eecs.umich.edu class Mul1s(WrRegOp): 5479699Snilay@cs.wisc.edu op_class = 'IntMultOp' 5489699Snilay@cs.wisc.edu 5495040Sgblack@eecs.umich.edu code = ''' 5505063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5515063Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5526742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5536430Sgblack@eecs.umich.edu uint64_t hiResult; 5546430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5556430Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5566461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5576430Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5586430Sgblack@eecs.umich.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5596430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5606430Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5616462Sgblack@eecs.umich.edu if (bits(psrc1, dataSize * 8 - 1)) 5626430Sgblack@eecs.umich.edu hiResult -= op2; 5636462Sgblack@eecs.umich.edu if (bits(op2, dataSize * 8 - 1)) 5646430Sgblack@eecs.umich.edu hiResult -= psrc1; 5656430Sgblack@eecs.umich.edu ProdHi = hiResult; 5665040Sgblack@eecs.umich.edu ''' 5676463Sgblack@eecs.umich.edu flag_code = ''' 5686463Sgblack@eecs.umich.edu if ((-ProdHi & mask(dataSize * 8)) != 5696463Sgblack@eecs.umich.edu bits(ProdLow, dataSize * 8 - 1)) { 5709212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 5719212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 5726463Sgblack@eecs.umich.edu } else { 5739212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 5749212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 5756463Sgblack@eecs.umich.edu } 5766463Sgblack@eecs.umich.edu ''' 5775040Sgblack@eecs.umich.edu 5785063Sgblack@eecs.umich.edu class Mul1u(WrRegOp): 5799699Snilay@cs.wisc.edu op_class = 'IntMultOp' 5809699Snilay@cs.wisc.edu 5815040Sgblack@eecs.umich.edu code = ''' 5825063Sgblack@eecs.umich.edu ProdLow = psrc1 * op2; 5834809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5846742Svince@csl.cornell.edu uint64_t shifter = (ULL(1) << halfSize); 5856430Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5865063Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5876461Sgblack@eecs.umich.edu uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 5885063Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5895063Sgblack@eecs.umich.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5906430Sgblack@eecs.umich.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5915063Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5925040Sgblack@eecs.umich.edu ''' 5936463Sgblack@eecs.umich.edu flag_code = ''' 5946463Sgblack@eecs.umich.edu if (ProdHi) { 5959212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit | OFBit)); 5969212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 5976463Sgblack@eecs.umich.edu } else { 5989212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 5999212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 6006463Sgblack@eecs.umich.edu } 6016463Sgblack@eecs.umich.edu ''' 6025040Sgblack@eecs.umich.edu 6035063Sgblack@eecs.umich.edu class Mulel(RdRegOp): 6045063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 6057967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdLow & mask(dataSize * 8);' 6065040Sgblack@eecs.umich.edu 6075063Sgblack@eecs.umich.edu class Muleh(RdRegOp): 6085063Sgblack@eecs.umich.edu def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 6095063Sgblack@eecs.umich.edu if not src1: 6105063Sgblack@eecs.umich.edu src1 = dest 6116345Sgblack@eecs.umich.edu super(RdRegOp, self).__init__(dest, src1, \ 6126345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 6135063Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 6147967Sgblack@eecs.umich.edu big_code = 'DestReg = ProdHi & mask(dataSize * 8);' 6155062Sgblack@eecs.umich.edu 6165075Sgblack@eecs.umich.edu # One or two bit divide 6175075Sgblack@eecs.umich.edu class Div1(WrRegOp): 6189699Snilay@cs.wisc.edu op_class = 'IntDivOp' 6199699Snilay@cs.wisc.edu 6205040Sgblack@eecs.umich.edu code = ''' 6215075Sgblack@eecs.umich.edu //These are temporaries so that modifying them later won't make 6225075Sgblack@eecs.umich.edu //the ISA parser think they're also sources. 6235075Sgblack@eecs.umich.edu uint64_t quotient = 0; 6245075Sgblack@eecs.umich.edu uint64_t remainder = psrc1; 6255075Sgblack@eecs.umich.edu //Similarly, this is a temporary so changing it doesn't make it 6265075Sgblack@eecs.umich.edu //a source. 6275075Sgblack@eecs.umich.edu uint64_t divisor = op2; 6285075Sgblack@eecs.umich.edu //This is a temporary just for consistency and clarity. 6295075Sgblack@eecs.umich.edu uint64_t dividend = remainder; 6305075Sgblack@eecs.umich.edu //Do the division. 6317719Sgblack@eecs.umich.edu if (divisor == 0) { 6327719Sgblack@eecs.umich.edu fault = new DivideByZero; 6337719Sgblack@eecs.umich.edu } else { 6347719Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6357719Sgblack@eecs.umich.edu //Record the final results. 6367719Sgblack@eecs.umich.edu Remainder = remainder; 6377719Sgblack@eecs.umich.edu Quotient = quotient; 6387719Sgblack@eecs.umich.edu Divisor = divisor; 6397719Sgblack@eecs.umich.edu } 6405040Sgblack@eecs.umich.edu ''' 6414823Sgblack@eecs.umich.edu 6425075Sgblack@eecs.umich.edu # Step divide 6435075Sgblack@eecs.umich.edu class Div2(RegOp): 6449699Snilay@cs.wisc.edu op_class = 'IntDivOp' 6459699Snilay@cs.wisc.edu 6467967Sgblack@eecs.umich.edu divCode = ''' 6475075Sgblack@eecs.umich.edu uint64_t dividend = Remainder; 6485075Sgblack@eecs.umich.edu uint64_t divisor = Divisor; 6495075Sgblack@eecs.umich.edu uint64_t quotient = Quotient; 6505075Sgblack@eecs.umich.edu uint64_t remainder = dividend; 6515075Sgblack@eecs.umich.edu int remaining = op2; 6525075Sgblack@eecs.umich.edu //If we overshot, do nothing. This lets us unrool division loops a 6535075Sgblack@eecs.umich.edu //little. 6547719Sgblack@eecs.umich.edu if (divisor == 0) { 6557719Sgblack@eecs.umich.edu fault = new DivideByZero; 6567719Sgblack@eecs.umich.edu } else if (remaining) { 6577070Sgblack@eecs.umich.edu if (divisor & (ULL(1) << 63)) { 6587070Sgblack@eecs.umich.edu while (remaining && !(dividend & (ULL(1) << 63))) { 6597070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6607070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6617070Sgblack@eecs.umich.edu quotient <<= 1; 6627070Sgblack@eecs.umich.edu remaining--; 6637070Sgblack@eecs.umich.edu } 6647070Sgblack@eecs.umich.edu if (dividend & (ULL(1) << 63)) { 6657080Sgblack@eecs.umich.edu bool highBit = false; 6667070Sgblack@eecs.umich.edu if (dividend < divisor && remaining) { 6677080Sgblack@eecs.umich.edu highBit = true; 6687070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6697070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6707070Sgblack@eecs.umich.edu quotient <<= 1; 6717070Sgblack@eecs.umich.edu remaining--; 6727070Sgblack@eecs.umich.edu } 6737080Sgblack@eecs.umich.edu if (highBit || divisor <= dividend) { 6747080Sgblack@eecs.umich.edu quotient++; 6757080Sgblack@eecs.umich.edu dividend -= divisor; 6767080Sgblack@eecs.umich.edu } 6777070Sgblack@eecs.umich.edu } 6787070Sgblack@eecs.umich.edu remainder = dividend; 6797070Sgblack@eecs.umich.edu } else { 6807070Sgblack@eecs.umich.edu //Shift in bits from the low order portion of the dividend 6817070Sgblack@eecs.umich.edu while (dividend < divisor && remaining) { 6827070Sgblack@eecs.umich.edu dividend = (dividend << 1) | 6837070Sgblack@eecs.umich.edu bits(SrcReg1, remaining - 1); 6847070Sgblack@eecs.umich.edu quotient <<= 1; 6857070Sgblack@eecs.umich.edu remaining--; 6867070Sgblack@eecs.umich.edu } 6877070Sgblack@eecs.umich.edu remainder = dividend; 6887070Sgblack@eecs.umich.edu //Do the division. 6897070Sgblack@eecs.umich.edu divide(dividend, divisor, quotient, remainder); 6905075Sgblack@eecs.umich.edu } 6915075Sgblack@eecs.umich.edu } 6925075Sgblack@eecs.umich.edu //Keep track of how many bits there are still to pull in. 6937967Sgblack@eecs.umich.edu %s 6945075Sgblack@eecs.umich.edu //Record the final results 6955075Sgblack@eecs.umich.edu Remainder = remainder; 6965075Sgblack@eecs.umich.edu Quotient = quotient; 6975075Sgblack@eecs.umich.edu ''' 6987967Sgblack@eecs.umich.edu code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" 6997967Sgblack@eecs.umich.edu big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" 7005075Sgblack@eecs.umich.edu flag_code = ''' 7017480Sgblack@eecs.umich.edu if (remaining == 0) 7029212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 7035075Sgblack@eecs.umich.edu else 7049212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 7055075Sgblack@eecs.umich.edu ''' 7064732Sgblack@eecs.umich.edu 7075075Sgblack@eecs.umich.edu class Divq(RdRegOp): 7085075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 7097967Sgblack@eecs.umich.edu big_code = 'DestReg = Quotient & mask(dataSize * 8);' 7105075Sgblack@eecs.umich.edu 7115075Sgblack@eecs.umich.edu class Divr(RdRegOp): 7125075Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 7137967Sgblack@eecs.umich.edu big_code = 'DestReg = Remainder & mask(dataSize * 8);' 7145040Sgblack@eecs.umich.edu 7155040Sgblack@eecs.umich.edu class Mov(CondRegOp): 7165040Sgblack@eecs.umich.edu code = 'DestReg = merge(SrcReg1, op2, dataSize)' 7176482Sgblack@eecs.umich.edu else_code = 'DestReg = DestReg;' 7185040Sgblack@eecs.umich.edu 7194732Sgblack@eecs.umich.edu # Shift instructions 7205040Sgblack@eecs.umich.edu 7215076Sgblack@eecs.umich.edu class Sll(RegOp): 7225040Sgblack@eecs.umich.edu code = ''' 7234756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7244823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 7255040Sgblack@eecs.umich.edu ''' 7267967Sgblack@eecs.umich.edu big_code = ''' 7277967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7287967Sgblack@eecs.umich.edu DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); 7297967Sgblack@eecs.umich.edu ''' 7305076Sgblack@eecs.umich.edu flag_code = ''' 7315076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7325076Sgblack@eecs.umich.edu if (shiftAmt) { 7335076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7345076Sgblack@eecs.umich.edu //worry about setting them. 7359212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 7369212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 7379010Snilay@cs.wisc.edu 7385076Sgblack@eecs.umich.edu int CFBits = 0; 7395076Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 7406441Sgblack@eecs.umich.edu if (shiftAmt <= dataSize * 8 && 7416441Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 7425076Sgblack@eecs.umich.edu CFBits = 1; 7436441Sgblack@eecs.umich.edu } 7449010Snilay@cs.wisc.edu 7455076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7469010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 7479212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 7489212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 7499010Snilay@cs.wisc.edu } 7509010Snilay@cs.wisc.edu 7515076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7525076Sgblack@eecs.umich.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 7539212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 7549010Snilay@cs.wisc.edu 7555076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 7569212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 7579212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 7589212Snilay@cs.wisc.edu DestReg, psrc1, op2); 7599212Snilay@cs.wisc.edu 7609212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 7619212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 7629212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 7635076Sgblack@eecs.umich.edu } 7645076Sgblack@eecs.umich.edu ''' 7655040Sgblack@eecs.umich.edu 7665076Sgblack@eecs.umich.edu class Srl(RegOp): 7677967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 7687967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to mask them out 7697967Sgblack@eecs.umich.edu # to be sure they're zero. 7705040Sgblack@eecs.umich.edu code = ''' 7714756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7724732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7734823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 7745040Sgblack@eecs.umich.edu ''' 7757967Sgblack@eecs.umich.edu big_code = ''' 7767967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7777967Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 7787967Sgblack@eecs.umich.edu DestReg = (psrc1 >> shiftAmt) & logicalMask; 7797967Sgblack@eecs.umich.edu ''' 7805076Sgblack@eecs.umich.edu flag_code = ''' 7815076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 7825076Sgblack@eecs.umich.edu if (shiftAmt) { 7835076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 7845076Sgblack@eecs.umich.edu //worry about setting them. 7859212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 7869212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 7879010Snilay@cs.wisc.edu 7885076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 7896442Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 7906442Sgblack@eecs.umich.edu shiftAmt <= dataSize * 8 && 7916442Sgblack@eecs.umich.edu bits(SrcReg1, shiftAmt - 1)) { 7929212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 7939212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 7946442Sgblack@eecs.umich.edu } 7959010Snilay@cs.wisc.edu 7965076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 7975076Sgblack@eecs.umich.edu if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 7989212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 7999010Snilay@cs.wisc.edu 8005076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8019212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8029212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8039212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8049212Snilay@cs.wisc.edu 8059212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8069212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8079212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8085076Sgblack@eecs.umich.edu } 8095076Sgblack@eecs.umich.edu ''' 8105040Sgblack@eecs.umich.edu 8115076Sgblack@eecs.umich.edu class Sra(RegOp): 8127967Sgblack@eecs.umich.edu # Because what happens to the bits shift -in- on a right shift 8137967Sgblack@eecs.umich.edu # is not defined in the C/C++ standard, we have to sign extend 8147967Sgblack@eecs.umich.edu # them manually to be sure. 8155040Sgblack@eecs.umich.edu code = ''' 8164756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8176443Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8185032Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8194823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 8205040Sgblack@eecs.umich.edu ''' 8217967Sgblack@eecs.umich.edu big_code = ''' 8227967Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8237967Sgblack@eecs.umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 8247967Sgblack@eecs.umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 8257967Sgblack@eecs.umich.edu DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); 8267967Sgblack@eecs.umich.edu ''' 8275076Sgblack@eecs.umich.edu flag_code = ''' 8285076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8295076Sgblack@eecs.umich.edu if (shiftAmt) { 8305076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8315076Sgblack@eecs.umich.edu //worry about setting them. 8329212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8339212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8349010Snilay@cs.wisc.edu 8355076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8366444Sgblack@eecs.umich.edu uint8_t effectiveShift = 8376444Sgblack@eecs.umich.edu (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 8386444Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 8396444Sgblack@eecs.umich.edu bits(SrcReg1, effectiveShift - 1)) { 8409212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8419212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8426444Sgblack@eecs.umich.edu } 8439010Snilay@cs.wisc.edu 8445076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8459212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8469212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8479212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8489212Snilay@cs.wisc.edu 8499212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8509212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8519212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8525076Sgblack@eecs.umich.edu } 8535076Sgblack@eecs.umich.edu ''' 8545040Sgblack@eecs.umich.edu 8555076Sgblack@eecs.umich.edu class Ror(RegOp): 8565040Sgblack@eecs.umich.edu code = ''' 8574732Sgblack@eecs.umich.edu uint8_t shiftAmt = 8584756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 8596449Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 8607967Sgblack@eecs.umich.edu if (realShiftAmt) { 8616449Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 8626449Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 8634732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 8647967Sgblack@eecs.umich.edu } else 8656447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 8665040Sgblack@eecs.umich.edu ''' 8675076Sgblack@eecs.umich.edu flag_code = ''' 8685076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 8695076Sgblack@eecs.umich.edu if (shiftAmt) { 8705076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 8715076Sgblack@eecs.umich.edu //worry about setting them. 8729212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 8739212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 8749010Snilay@cs.wisc.edu 8755076Sgblack@eecs.umich.edu //Find the most and second most significant bits of the result. 8765076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 8775076Sgblack@eecs.umich.edu int smsb = bits(DestReg, dataSize * 8 - 2); 8785076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 8799010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && msb) { 8809212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 8819212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 8829010Snilay@cs.wisc.edu } 8839010Snilay@cs.wisc.edu 8845076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 8855076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ smsb)) 8869212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 8879010Snilay@cs.wisc.edu 8885076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 8899212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 8909212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 8919212Snilay@cs.wisc.edu DestReg, psrc1, op2); 8929212Snilay@cs.wisc.edu 8939212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 8949212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 8959212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 8965076Sgblack@eecs.umich.edu } 8975076Sgblack@eecs.umich.edu ''' 8985040Sgblack@eecs.umich.edu 8995076Sgblack@eecs.umich.edu class Rcr(RegOp): 9005040Sgblack@eecs.umich.edu code = ''' 9014733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9024756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9036454Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9047967Sgblack@eecs.umich.edu if (realShiftAmt) { 9059010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9066454Sgblack@eecs.umich.edu uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 9076454Sgblack@eecs.umich.edu if (realShiftAmt > 1) 9086454Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 9096454Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 9104733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9117967Sgblack@eecs.umich.edu } else 9126447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9135040Sgblack@eecs.umich.edu ''' 9145076Sgblack@eecs.umich.edu flag_code = ''' 9155076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9165076Sgblack@eecs.umich.edu if (shiftAmt) { 9179010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 9185076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9195076Sgblack@eecs.umich.edu //worry about setting them. 9209212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9219212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9229010Snilay@cs.wisc.edu 9235076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9246453Sgblack@eecs.umich.edu if ((ext & OFBit) && (origCFBit ^ 9256453Sgblack@eecs.umich.edu bits(SrcReg1, dataSize * 8 - 1))) { 9269212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9276453Sgblack@eecs.umich.edu } 9285076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9296454Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 9306454Sgblack@eecs.umich.edu (realShiftAmt == 0) ? origCFBit : 9316454Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) { 9329212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9339212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9346454Sgblack@eecs.umich.edu } 9359010Snilay@cs.wisc.edu 9365076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9379212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9389212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9399212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9409212Snilay@cs.wisc.edu 9419212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9429212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9439212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9445076Sgblack@eecs.umich.edu } 9455076Sgblack@eecs.umich.edu ''' 9465040Sgblack@eecs.umich.edu 9475076Sgblack@eecs.umich.edu class Rol(RegOp): 9485040Sgblack@eecs.umich.edu code = ''' 9494732Sgblack@eecs.umich.edu uint8_t shiftAmt = 9504756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9516446Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 9527967Sgblack@eecs.umich.edu if (realShiftAmt) { 9536446Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 9544732Sgblack@eecs.umich.edu uint64_t bottom = 9556446Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 9564732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 9577967Sgblack@eecs.umich.edu } else 9586447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 9595040Sgblack@eecs.umich.edu ''' 9605076Sgblack@eecs.umich.edu flag_code = ''' 9615076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 9625076Sgblack@eecs.umich.edu if (shiftAmt) { 9635076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 9645076Sgblack@eecs.umich.edu //worry about setting them. 9659212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 9669212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 9679010Snilay@cs.wisc.edu 9685076Sgblack@eecs.umich.edu //The CF bits, if set, would be set to the lsb of the result. 9695076Sgblack@eecs.umich.edu int lsb = DestReg & 0x1; 9705076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 9715076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 9729010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && lsb) { 9739212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 9749212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 9759010Snilay@cs.wisc.edu } 9769010Snilay@cs.wisc.edu 9775076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 9785076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ lsb)) 9799212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 9809010Snilay@cs.wisc.edu 9815076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 9829212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 9839212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 9849212Snilay@cs.wisc.edu DestReg, psrc1, op2); 9859212Snilay@cs.wisc.edu 9869212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 9879212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 9889212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 9895076Sgblack@eecs.umich.edu } 9905076Sgblack@eecs.umich.edu ''' 9915040Sgblack@eecs.umich.edu 9925076Sgblack@eecs.umich.edu class Rcl(RegOp): 9935040Sgblack@eecs.umich.edu code = ''' 9944733Sgblack@eecs.umich.edu uint8_t shiftAmt = 9954756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 9966456Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 9977967Sgblack@eecs.umich.edu if (realShiftAmt) { 9989010Snilay@cs.wisc.edu CCFlagBits flags = cfofBits; 9996456Sgblack@eecs.umich.edu uint64_t top = psrc1 << realShiftAmt; 10006456Sgblack@eecs.umich.edu uint64_t bottom = flags.cf << (realShiftAmt - 1); 10014733Sgblack@eecs.umich.edu if(shiftAmt > 1) 10024733Sgblack@eecs.umich.edu bottom |= 10034823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 10046456Sgblack@eecs.umich.edu dataSize * 8 - realShiftAmt + 1); 10054733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 10067967Sgblack@eecs.umich.edu } else 10076447Sgblack@eecs.umich.edu DestReg = merge(DestReg, DestReg, dataSize); 10085040Sgblack@eecs.umich.edu ''' 10095076Sgblack@eecs.umich.edu flag_code = ''' 10105076Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10115076Sgblack@eecs.umich.edu if (shiftAmt) { 10129010Snilay@cs.wisc.edu int origCFBit = (cfofBits & CFBit) ? 1 : 0; 10135076Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10145076Sgblack@eecs.umich.edu //worry about setting them. 10159212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10169212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10179010Snilay@cs.wisc.edu 10185076Sgblack@eecs.umich.edu int msb = bits(DestReg, dataSize * 8 - 1); 10196456Sgblack@eecs.umich.edu int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 10205076Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10216456Sgblack@eecs.umich.edu if ((ext & (CFBit | ECFBit)) && 10229010Snilay@cs.wisc.edu (realShiftAmt == 0) ? origCFBit : CFBits) { 10239212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10249212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10259010Snilay@cs.wisc.edu } 10269010Snilay@cs.wisc.edu 10275076Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10285076Sgblack@eecs.umich.edu if ((ext & OFBit) && (msb ^ CFBits)) 10299212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10309010Snilay@cs.wisc.edu 10315076Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10329212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10339212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10349212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10359212Snilay@cs.wisc.edu 10369212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10379212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10389212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10395076Sgblack@eecs.umich.edu } 10405076Sgblack@eecs.umich.edu ''' 10414732Sgblack@eecs.umich.edu 10426479Sgblack@eecs.umich.edu class Sld(RegOp): 10437967Sgblack@eecs.umich.edu sldCode = ''' 10446479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 10456479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 10467967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 10476479Sgblack@eecs.umich.edu uint64_t result; 10486479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 10496479Sgblack@eecs.umich.edu result = psrc1; 10506479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 10516479Sgblack@eecs.umich.edu result = (psrc1 << realShiftAmt) | 10526479Sgblack@eecs.umich.edu (DoubleBits >> (dataBits - realShiftAmt)); 10536479Sgblack@eecs.umich.edu } else { 10546479Sgblack@eecs.umich.edu result = (DoubleBits << (realShiftAmt - dataBits)) | 10556479Sgblack@eecs.umich.edu (psrc1 >> (2 * dataBits - realShiftAmt)); 10566479Sgblack@eecs.umich.edu } 10577967Sgblack@eecs.umich.edu %s 10586479Sgblack@eecs.umich.edu ''' 10597967Sgblack@eecs.umich.edu code = sldCode % "DestReg = merge(DestReg, result, dataSize);" 10607967Sgblack@eecs.umich.edu big_code = sldCode % "DestReg = result & mask(dataSize * 8);" 10616479Sgblack@eecs.umich.edu flag_code = ''' 10626479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 10636479Sgblack@eecs.umich.edu if (shiftAmt) { 10646479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 10656479Sgblack@eecs.umich.edu //worry about setting them. 10669212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 10679212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 10686479Sgblack@eecs.umich.edu int CFBits = 0; 10699010Snilay@cs.wisc.edu 10706479Sgblack@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 10716479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 10726479Sgblack@eecs.umich.edu bits(DoubleBits, 0)) || 10736479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 10746479Sgblack@eecs.umich.edu bits(SrcReg1, dataBits - realShiftAmt)) || 10756479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 10766479Sgblack@eecs.umich.edu bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 10776479Sgblack@eecs.umich.edu CFBits = 1; 10786479Sgblack@eecs.umich.edu } 10799010Snilay@cs.wisc.edu 10806479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 10819010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 10829212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 10839212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 10849010Snilay@cs.wisc.edu } 10859010Snilay@cs.wisc.edu 10866479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 10876479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 10886479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 10899212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 10909010Snilay@cs.wisc.edu 10916479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 10929212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 10939212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 10949212Snilay@cs.wisc.edu DestReg, psrc1, op2); 10959212Snilay@cs.wisc.edu 10969212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 10979212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 10989212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 10996479Sgblack@eecs.umich.edu } 11006479Sgblack@eecs.umich.edu ''' 11016479Sgblack@eecs.umich.edu 11026479Sgblack@eecs.umich.edu class Srd(RegOp): 11037967Sgblack@eecs.umich.edu srdCode = ''' 11046479Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 11056479Sgblack@eecs.umich.edu uint8_t dataBits = dataSize * 8; 11067967Sgblack@eecs.umich.edu uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); 11076479Sgblack@eecs.umich.edu uint64_t result; 11086479Sgblack@eecs.umich.edu if (realShiftAmt == 0) { 11096479Sgblack@eecs.umich.edu result = psrc1; 11106479Sgblack@eecs.umich.edu } else if (realShiftAmt < dataBits) { 11116479Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right 11126479Sgblack@eecs.umich.edu // shift is not defined in the C/C++ standard, we have to 11136479Sgblack@eecs.umich.edu // mask them out to be sure they're zero. 11146479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataBits - realShiftAmt); 11156479Sgblack@eecs.umich.edu result = ((psrc1 >> realShiftAmt) & logicalMask) | 11166479Sgblack@eecs.umich.edu (DoubleBits << (dataBits - realShiftAmt)); 11176479Sgblack@eecs.umich.edu } else { 11186479Sgblack@eecs.umich.edu uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 11196479Sgblack@eecs.umich.edu result = ((DoubleBits >> (realShiftAmt - dataBits)) & 11206479Sgblack@eecs.umich.edu logicalMask) | 11216479Sgblack@eecs.umich.edu (psrc1 << (2 * dataBits - realShiftAmt)); 11226479Sgblack@eecs.umich.edu } 11237967Sgblack@eecs.umich.edu %s 11246479Sgblack@eecs.umich.edu ''' 11257967Sgblack@eecs.umich.edu code = srdCode % "DestReg = merge(DestReg, result, dataSize);" 11267967Sgblack@eecs.umich.edu big_code = srdCode % "DestReg = result & mask(dataSize * 8);" 11276479Sgblack@eecs.umich.edu flag_code = ''' 11286479Sgblack@eecs.umich.edu // If the shift amount is zero, no flags should be modified. 11296479Sgblack@eecs.umich.edu if (shiftAmt) { 11306479Sgblack@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 11316479Sgblack@eecs.umich.edu //worry about setting them. 11329212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit)); 11339212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 11346479Sgblack@eecs.umich.edu int CFBits = 0; 11359010Snilay@cs.wisc.edu 11366479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11376479Sgblack@eecs.umich.edu if ((realShiftAmt == 0 && 11386479Sgblack@eecs.umich.edu bits(DoubleBits, dataBits - 1)) || 11396479Sgblack@eecs.umich.edu (realShiftAmt <= dataBits && 11406479Sgblack@eecs.umich.edu bits(SrcReg1, realShiftAmt - 1)) || 11416479Sgblack@eecs.umich.edu (realShiftAmt > dataBits && 11426479Sgblack@eecs.umich.edu bits(DoubleBits, realShiftAmt - dataBits - 1))) { 11436479Sgblack@eecs.umich.edu CFBits = 1; 11446479Sgblack@eecs.umich.edu } 11459010Snilay@cs.wisc.edu 11466479Sgblack@eecs.umich.edu //If some combination of the CF bits need to be set, set them. 11479010Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && CFBits) { 11489212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & CFBit); 11499212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 11509010Snilay@cs.wisc.edu } 11519010Snilay@cs.wisc.edu 11526479Sgblack@eecs.umich.edu //Figure out what the OF bit should be. 11536479Sgblack@eecs.umich.edu if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 11546479Sgblack@eecs.umich.edu bits(result, dataBits - 1))) 11559212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | OFBit; 11569010Snilay@cs.wisc.edu 11576479Sgblack@eecs.umich.edu //Use the regular mechanisms to calculate the other flags. 11589212Snilay@cs.wisc.edu uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit | 11599212Snilay@cs.wisc.edu PredezfBit, ext & ~(CFBit | ECFBit | OFBit), 11609212Snilay@cs.wisc.edu DestReg, psrc1, op2); 11619212Snilay@cs.wisc.edu 11629212Snilay@cs.wisc.edu PredezfBit = newFlags & EZFBit; 11639212Snilay@cs.wisc.edu PreddfBit = newFlags & DFBit; 11649212Snilay@cs.wisc.edu PredccFlagBits = newFlags & ccFlagMask; 11656479Sgblack@eecs.umich.edu } 11666479Sgblack@eecs.umich.edu ''' 11676479Sgblack@eecs.umich.edu 11686479Sgblack@eecs.umich.edu class Mdb(WrRegOp): 11696479Sgblack@eecs.umich.edu code = 'DoubleBits = psrc1 ^ op2;' 11706479Sgblack@eecs.umich.edu 11715040Sgblack@eecs.umich.edu class Wrip(WrRegOp, CondRegOp): 11727789Sgblack@eecs.umich.edu code = 'NRIP = psrc1 + sop2 + CSBase;' 11737789Sgblack@eecs.umich.edu else_code = "NRIP = NRIP;" 11745040Sgblack@eecs.umich.edu 11755040Sgblack@eecs.umich.edu class Wruflags(WrRegOp): 11769010Snilay@cs.wisc.edu code = ''' 11779010Snilay@cs.wisc.edu uint64_t newFlags = psrc1 ^ op2; 11789010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11799010Snilay@cs.wisc.edu ecfBit = newFlags & ECFBit; 11809010Snilay@cs.wisc.edu ezfBit = newFlags & EZFBit; 11819211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11829010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11839010Snilay@cs.wisc.edu ''' 11845040Sgblack@eecs.umich.edu 11855426Sgblack@eecs.umich.edu class Wrflags(WrRegOp): 11865426Sgblack@eecs.umich.edu code = ''' 11875426Sgblack@eecs.umich.edu MiscReg newFlags = psrc1 ^ op2; 11885426Sgblack@eecs.umich.edu MiscReg userFlagMask = 0xDD5; 11899010Snilay@cs.wisc.edu 11905426Sgblack@eecs.umich.edu // Get only the user flags 11919010Snilay@cs.wisc.edu ccFlagBits = newFlags & ccFlagMask; 11929211Snilay@cs.wisc.edu dfBit = newFlags & DFBit; 11939010Snilay@cs.wisc.edu cfofBits = newFlags & cfofMask; 11949010Snilay@cs.wisc.edu ecfBit = 0; 11959010Snilay@cs.wisc.edu ezfBit = 0; 11969010Snilay@cs.wisc.edu 11975426Sgblack@eecs.umich.edu // Get everything else 11985426Sgblack@eecs.umich.edu nccFlagBits = newFlags & ~userFlagMask; 11995426Sgblack@eecs.umich.edu ''' 12005426Sgblack@eecs.umich.edu 12015040Sgblack@eecs.umich.edu class Rdip(RdRegOp): 12027789Sgblack@eecs.umich.edu code = 'DestReg = NRIP - CSBase;' 12035040Sgblack@eecs.umich.edu 12045040Sgblack@eecs.umich.edu class Ruflags(RdRegOp): 12059211Snilay@cs.wisc.edu code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;' 12065040Sgblack@eecs.umich.edu 12075426Sgblack@eecs.umich.edu class Rflags(RdRegOp): 12089010Snilay@cs.wisc.edu code = ''' 12099211Snilay@cs.wisc.edu DestReg = ccFlagBits | cfofBits | dfBit | 12109211Snilay@cs.wisc.edu ecfBit | ezfBit | nccFlagBits; 12119010Snilay@cs.wisc.edu ''' 12125426Sgblack@eecs.umich.edu 12135040Sgblack@eecs.umich.edu class Ruflag(RegOp): 12145040Sgblack@eecs.umich.edu code = ''' 12159211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12169211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12174951Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12189010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12195040Sgblack@eecs.umich.edu ''' 12209010Snilay@cs.wisc.edu 12217967Sgblack@eecs.umich.edu big_code = ''' 12229211Snilay@cs.wisc.edu int flag = bits(ccFlagBits | cfofBits | dfBit | 12239211Snilay@cs.wisc.edu ecfBit | ezfBit, imm8); 12247967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12259010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12267967Sgblack@eecs.umich.edu ''' 12279010Snilay@cs.wisc.edu 12285040Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12295040Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12305040Sgblack@eecs.umich.edu super(Ruflag, self).__init__(dest, \ 12316345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12324732Sgblack@eecs.umich.edu 12335426Sgblack@eecs.umich.edu class Rflag(RegOp): 12345426Sgblack@eecs.umich.edu code = ''' 12355426Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12369211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12379010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12389010Snilay@cs.wisc.edu 12395426Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12405426Sgblack@eecs.umich.edu DestReg = merge(DestReg, flag, dataSize); 12419010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12425426Sgblack@eecs.umich.edu ''' 12439010Snilay@cs.wisc.edu 12447967Sgblack@eecs.umich.edu big_code = ''' 12457967Sgblack@eecs.umich.edu MiscReg flagMask = 0x3F7FDD5; 12469211Snilay@cs.wisc.edu MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | dfBit | 12479010Snilay@cs.wisc.edu ecfBit | ezfBit) & flagMask; 12489010Snilay@cs.wisc.edu 12497967Sgblack@eecs.umich.edu int flag = bits(flags, imm8); 12507967Sgblack@eecs.umich.edu DestReg = flag & mask(dataSize * 8); 12519010Snilay@cs.wisc.edu ezfBit = (flag == 0) ? EZFBit : 0; 12527967Sgblack@eecs.umich.edu ''' 12539010Snilay@cs.wisc.edu 12545426Sgblack@eecs.umich.edu def __init__(self, dest, imm, flags=None, \ 12555426Sgblack@eecs.umich.edu dataSize="env.dataSize"): 12565426Sgblack@eecs.umich.edu super(Rflag, self).__init__(dest, \ 12576345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 12585426Sgblack@eecs.umich.edu 12595040Sgblack@eecs.umich.edu class Sext(RegOp): 12605040Sgblack@eecs.umich.edu code = ''' 12614823Sgblack@eecs.umich.edu IntReg val = psrc1; 12625239Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12635239Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12645239Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12655239Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12665007Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12675007Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize); 12685040Sgblack@eecs.umich.edu ''' 12699010Snilay@cs.wisc.edu 12707967Sgblack@eecs.umich.edu big_code = ''' 12717967Sgblack@eecs.umich.edu IntReg val = psrc1; 12727967Sgblack@eecs.umich.edu // Mask the bit position so that it wraps. 12737967Sgblack@eecs.umich.edu int bitPos = op2 & (dataSize * 8 - 1); 12747967Sgblack@eecs.umich.edu int sign_bit = bits(val, bitPos, bitPos); 12757967Sgblack@eecs.umich.edu uint64_t maskVal = mask(bitPos+1); 12767967Sgblack@eecs.umich.edu val = sign_bit ? (val | ~maskVal) : (val & maskVal); 12777967Sgblack@eecs.umich.edu DestReg = val & mask(dataSize * 8); 12787967Sgblack@eecs.umich.edu ''' 12799010Snilay@cs.wisc.edu 12805239Sgblack@eecs.umich.edu flag_code = ''' 12819010Snilay@cs.wisc.edu if (!sign_bit) { 12829212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & (ZFBit)); 12839212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits & ~(ext & (CFBit)); 12849212Snilay@cs.wisc.edu PredecfBit = PredecfBit & ~(ext & ECFBit); 12859212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 12869010Snilay@cs.wisc.edu } else { 12879212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & (ZFBit)); 12889212Snilay@cs.wisc.edu PredcfofBits = PredcfofBits | (ext & (CFBit)); 12899212Snilay@cs.wisc.edu PredecfBit = PredecfBit | (ext & ECFBit); 12909212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 12919010Snilay@cs.wisc.edu } 12925239Sgblack@eecs.umich.edu ''' 12934714Sgblack@eecs.umich.edu 12945040Sgblack@eecs.umich.edu class Zext(RegOp): 12955927Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 12967967Sgblack@eecs.umich.edu big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' 12975241Sgblack@eecs.umich.edu 12985926Sgblack@eecs.umich.edu class Rddr(RegOp): 12995926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13005926Sgblack@eecs.umich.edu super(Rddr, self).__init__(dest, \ 13016345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13027967Sgblack@eecs.umich.edu rdrCode = ''' 13035926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 13045926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 13055926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 13065926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13075926Sgblack@eecs.umich.edu } else if (dr7.gd) { 13085926Sgblack@eecs.umich.edu fault = new DebugException(); 13095926Sgblack@eecs.umich.edu } else { 13107967Sgblack@eecs.umich.edu %s 13115926Sgblack@eecs.umich.edu } 13125926Sgblack@eecs.umich.edu ''' 13137967Sgblack@eecs.umich.edu code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" 13147967Sgblack@eecs.umich.edu big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" 13155926Sgblack@eecs.umich.edu 13165926Sgblack@eecs.umich.edu class Wrdr(RegOp): 13175926Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13185926Sgblack@eecs.umich.edu super(Wrdr, self).__init__(dest, \ 13196345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13205926Sgblack@eecs.umich.edu code = ''' 13215926Sgblack@eecs.umich.edu CR4 cr4 = CR4Op; 13225926Sgblack@eecs.umich.edu DR7 dr7 = DR7Op; 13235926Sgblack@eecs.umich.edu if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 13245926Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13256345Sgblack@eecs.umich.edu } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 13265926Sgblack@eecs.umich.edu machInst.mode.mode == LongMode) { 13275926Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13285926Sgblack@eecs.umich.edu } else if (dr7.gd) { 13295926Sgblack@eecs.umich.edu fault = new DebugException(); 13305926Sgblack@eecs.umich.edu } else { 13315926Sgblack@eecs.umich.edu DebugDest = psrc1; 13325926Sgblack@eecs.umich.edu } 13335926Sgblack@eecs.umich.edu ''' 13345926Sgblack@eecs.umich.edu 13355296Sgblack@eecs.umich.edu class Rdcr(RegOp): 13365296Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13375296Sgblack@eecs.umich.edu super(Rdcr, self).__init__(dest, \ 13386345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13397967Sgblack@eecs.umich.edu rdcrCode = ''' 13405924Sgblack@eecs.umich.edu if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 13415296Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13425296Sgblack@eecs.umich.edu } else { 13437967Sgblack@eecs.umich.edu %s 13445296Sgblack@eecs.umich.edu } 13455296Sgblack@eecs.umich.edu ''' 13467967Sgblack@eecs.umich.edu code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" 13477967Sgblack@eecs.umich.edu big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" 13485296Sgblack@eecs.umich.edu 13495241Sgblack@eecs.umich.edu class Wrcr(RegOp): 13505241Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 13515241Sgblack@eecs.umich.edu super(Wrcr, self).__init__(dest, \ 13526345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 13535241Sgblack@eecs.umich.edu code = ''' 13545241Sgblack@eecs.umich.edu if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 13555241Sgblack@eecs.umich.edu fault = new InvalidOpcode(); 13565241Sgblack@eecs.umich.edu } else { 13575241Sgblack@eecs.umich.edu // There are *s in the line below so it doesn't confuse the 13585241Sgblack@eecs.umich.edu // parser. They may be unnecessary. 13595241Sgblack@eecs.umich.edu //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 13605241Sgblack@eecs.umich.edu MiscReg newVal = psrc1; 13615241Sgblack@eecs.umich.edu 13625241Sgblack@eecs.umich.edu // Check for any modifications that would cause a fault. 13635241Sgblack@eecs.umich.edu switch(dest) { 13645241Sgblack@eecs.umich.edu case 0: 13655241Sgblack@eecs.umich.edu { 13665241Sgblack@eecs.umich.edu Efer efer = EferOp; 13675241Sgblack@eecs.umich.edu CR0 cr0 = newVal; 13685241Sgblack@eecs.umich.edu CR4 oldCr4 = CR4Op; 13695241Sgblack@eecs.umich.edu if (bits(newVal, 63, 32) || 13705241Sgblack@eecs.umich.edu (!cr0.pe && cr0.pg) || 13715241Sgblack@eecs.umich.edu (!cr0.cd && cr0.nw) || 13725241Sgblack@eecs.umich.edu (cr0.pg && efer.lme && !oldCr4.pae)) 13735241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13745241Sgblack@eecs.umich.edu } 13755241Sgblack@eecs.umich.edu break; 13765241Sgblack@eecs.umich.edu case 2: 13775241Sgblack@eecs.umich.edu break; 13785241Sgblack@eecs.umich.edu case 3: 13795241Sgblack@eecs.umich.edu break; 13805241Sgblack@eecs.umich.edu case 4: 13815241Sgblack@eecs.umich.edu { 13825241Sgblack@eecs.umich.edu CR4 cr4 = newVal; 13835241Sgblack@eecs.umich.edu // PAE can't be disabled in long mode. 13845241Sgblack@eecs.umich.edu if (bits(newVal, 63, 11) || 13855241Sgblack@eecs.umich.edu (machInst.mode.mode == LongMode && !cr4.pae)) 13865241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13875241Sgblack@eecs.umich.edu } 13885241Sgblack@eecs.umich.edu break; 13895241Sgblack@eecs.umich.edu case 8: 13905241Sgblack@eecs.umich.edu { 13915241Sgblack@eecs.umich.edu if (bits(newVal, 63, 4)) 13925241Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 13935241Sgblack@eecs.umich.edu } 13945241Sgblack@eecs.umich.edu default: 13958857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 13968857Sgblack@eecs.umich.edu "Unrecognized control register %d.\\n", dest); 13975241Sgblack@eecs.umich.edu } 13985241Sgblack@eecs.umich.edu ControlDest = newVal; 13995241Sgblack@eecs.umich.edu } 14005241Sgblack@eecs.umich.edu ''' 14015290Sgblack@eecs.umich.edu 14025294Sgblack@eecs.umich.edu # Microops for manipulating segmentation registers 14035672Sgblack@eecs.umich.edu class SegOp(CondRegOp): 14045294Sgblack@eecs.umich.edu abstract = True 14055290Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14065294Sgblack@eecs.umich.edu super(SegOp, self).__init__(dest, \ 14076345Sgblack@eecs.umich.edu src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14085294Sgblack@eecs.umich.edu 14095294Sgblack@eecs.umich.edu class Wrbase(SegOp): 14105290Sgblack@eecs.umich.edu code = ''' 14115294Sgblack@eecs.umich.edu SegBaseDest = psrc1; 14125290Sgblack@eecs.umich.edu ''' 14135290Sgblack@eecs.umich.edu 14145294Sgblack@eecs.umich.edu class Wrlimit(SegOp): 14155290Sgblack@eecs.umich.edu code = ''' 14165294Sgblack@eecs.umich.edu SegLimitDest = psrc1; 14175294Sgblack@eecs.umich.edu ''' 14185294Sgblack@eecs.umich.edu 14195294Sgblack@eecs.umich.edu class Wrsel(SegOp): 14205294Sgblack@eecs.umich.edu code = ''' 14215294Sgblack@eecs.umich.edu SegSelDest = psrc1; 14225294Sgblack@eecs.umich.edu ''' 14235294Sgblack@eecs.umich.edu 14245905Sgblack@eecs.umich.edu class WrAttr(SegOp): 14255905Sgblack@eecs.umich.edu code = ''' 14265905Sgblack@eecs.umich.edu SegAttrDest = psrc1; 14275905Sgblack@eecs.umich.edu ''' 14285905Sgblack@eecs.umich.edu 14295294Sgblack@eecs.umich.edu class Rdbase(SegOp): 14307967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' 14317967Sgblack@eecs.umich.edu big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' 14325294Sgblack@eecs.umich.edu 14335294Sgblack@eecs.umich.edu class Rdlimit(SegOp): 14347967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' 14357967Sgblack@eecs.umich.edu big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' 14365294Sgblack@eecs.umich.edu 14375427Sgblack@eecs.umich.edu class RdAttr(SegOp): 14387967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' 14397967Sgblack@eecs.umich.edu big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' 14405427Sgblack@eecs.umich.edu 14415294Sgblack@eecs.umich.edu class Rdsel(SegOp): 14427967Sgblack@eecs.umich.edu code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' 14437967Sgblack@eecs.umich.edu big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' 14445294Sgblack@eecs.umich.edu 14455682Sgblack@eecs.umich.edu class Rdval(RegOp): 14465682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14476345Sgblack@eecs.umich.edu super(Rdval, self).__init__(dest, src1, \ 14486345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14495682Sgblack@eecs.umich.edu code = ''' 14505682Sgblack@eecs.umich.edu DestReg = MiscRegSrc1; 14515682Sgblack@eecs.umich.edu ''' 14525682Sgblack@eecs.umich.edu 14535682Sgblack@eecs.umich.edu class Wrval(RegOp): 14545682Sgblack@eecs.umich.edu def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 14556345Sgblack@eecs.umich.edu super(Wrval, self).__init__(dest, src1, \ 14566345Sgblack@eecs.umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 14575682Sgblack@eecs.umich.edu code = ''' 14585682Sgblack@eecs.umich.edu MiscRegDest = SrcReg1; 14595682Sgblack@eecs.umich.edu ''' 14605682Sgblack@eecs.umich.edu 14615428Sgblack@eecs.umich.edu class Chks(RegOp): 14625428Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2=0, 14635428Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 14645428Sgblack@eecs.umich.edu super(Chks, self).__init__(dest, 14655428Sgblack@eecs.umich.edu src1, src2, flags, dataSize) 14665294Sgblack@eecs.umich.edu code = ''' 14675424Sgblack@eecs.umich.edu // The selector is in source 1 and can be at most 16 bits. 14685433Sgblack@eecs.umich.edu SegSelector selector = DestReg; 14695433Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 14705433Sgblack@eecs.umich.edu HandyM5Reg m5reg = M5Reg; 14715294Sgblack@eecs.umich.edu 14725428Sgblack@eecs.umich.edu switch (imm8) 14735428Sgblack@eecs.umich.edu { 14745428Sgblack@eecs.umich.edu case SegNoCheck: 14755428Sgblack@eecs.umich.edu break; 14765428Sgblack@eecs.umich.edu case SegCSCheck: 14776060Sgblack@eecs.umich.edu // Make sure it's the right type 14786060Sgblack@eecs.umich.edu if (desc.s == 0 || desc.type.codeOrData != 1) { 14796060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14806060Sgblack@eecs.umich.edu } else if (m5reg.cpl != desc.dpl) { 14816060Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 14826060Sgblack@eecs.umich.edu } 14835428Sgblack@eecs.umich.edu break; 14845428Sgblack@eecs.umich.edu case SegCallGateCheck: 14858857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("CS checks for far " 14868857Sgblack@eecs.umich.edu "calls/jumps through call gates not implemented.\\n"); 14875428Sgblack@eecs.umich.edu break; 14885855Sgblack@eecs.umich.edu case SegSoftIntGateCheck: 14895853Sgblack@eecs.umich.edu // Check permissions. 14905674Sgblack@eecs.umich.edu if (desc.dpl < m5reg.cpl) { 14915857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 14926058Sgblack@eecs.umich.edu break; 14935674Sgblack@eecs.umich.edu } 14945855Sgblack@eecs.umich.edu // Fall through on purpose 14955855Sgblack@eecs.umich.edu case SegIntGateCheck: 14965853Sgblack@eecs.umich.edu // Make sure the gate's the right type. 14975861Snate@binkert.org if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 14985853Sgblack@eecs.umich.edu ((desc.type & 0x6) != 0x6)) { 14995853Sgblack@eecs.umich.edu fault = new GeneralProtection(0); 15005853Sgblack@eecs.umich.edu } 15015674Sgblack@eecs.umich.edu break; 15025428Sgblack@eecs.umich.edu case SegSSCheck: 15035433Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 15045433Sgblack@eecs.umich.edu if (!desc.p) { 15055857Sgblack@eecs.umich.edu fault = new StackFault(selector); 15068626Sgblack@eecs.umich.edu } else if (!(desc.s == 1 && desc.type.codeOrData == 0 && 15078626Sgblack@eecs.umich.edu desc.type.w) || 15085433Sgblack@eecs.umich.edu (desc.dpl != m5reg.cpl) || 15095433Sgblack@eecs.umich.edu (selector.rpl != m5reg.cpl)) { 15105857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15115433Sgblack@eecs.umich.edu } 15128626Sgblack@eecs.umich.edu } else if (m5reg.submode != SixtyFourBitMode || 15138626Sgblack@eecs.umich.edu m5reg.cpl == 3) { 15148626Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15155433Sgblack@eecs.umich.edu } 15165428Sgblack@eecs.umich.edu break; 15175428Sgblack@eecs.umich.edu case SegIretCheck: 15185428Sgblack@eecs.umich.edu { 15195433Sgblack@eecs.umich.edu if ((!selector.si && !selector.ti) || 15205433Sgblack@eecs.umich.edu (selector.rpl < m5reg.cpl) || 15215433Sgblack@eecs.umich.edu !(desc.s == 1 && desc.type.codeOrData == 1) || 15225433Sgblack@eecs.umich.edu (!desc.type.c && desc.dpl != selector.rpl) || 15235679Sgblack@eecs.umich.edu (desc.type.c && desc.dpl > selector.rpl)) { 15245857Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15255679Sgblack@eecs.umich.edu } else if (!desc.p) { 15265857Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15275679Sgblack@eecs.umich.edu } 15285428Sgblack@eecs.umich.edu break; 15295428Sgblack@eecs.umich.edu } 15305428Sgblack@eecs.umich.edu case SegIntCSCheck: 15315675Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 15325675Sgblack@eecs.umich.edu if (desc.l != 1 || desc.d != 0) { 15335679Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15345675Sgblack@eecs.umich.edu } 15355675Sgblack@eecs.umich.edu } else { 15368857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault("Interrupt CS " 15378857Sgblack@eecs.umich.edu "checks not implemented in legacy mode.\\n"); 15385675Sgblack@eecs.umich.edu } 15395428Sgblack@eecs.umich.edu break; 15405899Sgblack@eecs.umich.edu case SegTRCheck: 15415899Sgblack@eecs.umich.edu if (!selector.si || selector.ti) { 15425899Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15435899Sgblack@eecs.umich.edu } 15445899Sgblack@eecs.umich.edu break; 15455900Sgblack@eecs.umich.edu case SegTSSCheck: 15465900Sgblack@eecs.umich.edu if (!desc.p) { 15475900Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15485900Sgblack@eecs.umich.edu } else if (!(desc.type == 0x9 || 15495900Sgblack@eecs.umich.edu (desc.type == 1 && 15505900Sgblack@eecs.umich.edu m5reg.mode != LongMode))) { 15515935Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15525900Sgblack@eecs.umich.edu } 15535900Sgblack@eecs.umich.edu break; 15545936Sgblack@eecs.umich.edu case SegInGDTCheck: 15555936Sgblack@eecs.umich.edu if (selector.ti) { 15565936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15575936Sgblack@eecs.umich.edu } 15585936Sgblack@eecs.umich.edu break; 15595936Sgblack@eecs.umich.edu case SegLDTCheck: 15605936Sgblack@eecs.umich.edu if (!desc.p) { 15615936Sgblack@eecs.umich.edu fault = new SegmentNotPresent(selector); 15625936Sgblack@eecs.umich.edu } else if (desc.type != 0x2) { 15635936Sgblack@eecs.umich.edu fault = new GeneralProtection(selector); 15645936Sgblack@eecs.umich.edu } 15655936Sgblack@eecs.umich.edu break; 15665428Sgblack@eecs.umich.edu default: 15678857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 15688857Sgblack@eecs.umich.edu "Undefined segment check type.\\n"); 15695428Sgblack@eecs.umich.edu } 15705294Sgblack@eecs.umich.edu ''' 15715294Sgblack@eecs.umich.edu flag_code = ''' 15725294Sgblack@eecs.umich.edu // Check for a NULL selector and set ZF,EZF appropriately. 15739212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits & ~(ext & ZFBit); 15749212Snilay@cs.wisc.edu PredezfBit = PredezfBit & ~(ext & EZFBit); 15759010Snilay@cs.wisc.edu 15769010Snilay@cs.wisc.edu if (!selector.si && !selector.ti) { 15779212Snilay@cs.wisc.edu PredccFlagBits = PredccFlagBits | (ext & ZFBit); 15789212Snilay@cs.wisc.edu PredezfBit = PredezfBit | (ext & EZFBit); 15799010Snilay@cs.wisc.edu } 15805294Sgblack@eecs.umich.edu ''' 15815294Sgblack@eecs.umich.edu 15825294Sgblack@eecs.umich.edu class Wrdh(RegOp): 15835294Sgblack@eecs.umich.edu code = ''' 15845678Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 15855294Sgblack@eecs.umich.edu 15865678Sgblack@eecs.umich.edu uint64_t target = bits(SrcReg2, 31, 0) << 32; 15875678Sgblack@eecs.umich.edu switch(desc.type) { 15885678Sgblack@eecs.umich.edu case LDT64: 15895678Sgblack@eecs.umich.edu case AvailableTSS64: 15905678Sgblack@eecs.umich.edu case BusyTSS64: 15915678Sgblack@eecs.umich.edu replaceBits(target, 23, 0, desc.baseLow); 15925678Sgblack@eecs.umich.edu replaceBits(target, 31, 24, desc.baseHigh); 15935678Sgblack@eecs.umich.edu break; 15945678Sgblack@eecs.umich.edu case CallGate64: 15955678Sgblack@eecs.umich.edu case IntGate64: 15965678Sgblack@eecs.umich.edu case TrapGate64: 15975678Sgblack@eecs.umich.edu replaceBits(target, 15, 0, bits(desc, 15, 0)); 15985678Sgblack@eecs.umich.edu replaceBits(target, 31, 16, bits(desc, 63, 48)); 15995678Sgblack@eecs.umich.edu break; 16005678Sgblack@eecs.umich.edu default: 16018857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16028857Sgblack@eecs.umich.edu "Wrdh used with wrong descriptor type!\\n"); 16035678Sgblack@eecs.umich.edu } 16045678Sgblack@eecs.umich.edu DestReg = target; 16055294Sgblack@eecs.umich.edu ''' 16065294Sgblack@eecs.umich.edu 16075409Sgblack@eecs.umich.edu class Wrtsc(WrRegOp): 16085409Sgblack@eecs.umich.edu code = ''' 16095409Sgblack@eecs.umich.edu TscOp = psrc1; 16105409Sgblack@eecs.umich.edu ''' 16115409Sgblack@eecs.umich.edu 16125409Sgblack@eecs.umich.edu class Rdtsc(RdRegOp): 16135409Sgblack@eecs.umich.edu code = ''' 16145409Sgblack@eecs.umich.edu DestReg = TscOp; 16155409Sgblack@eecs.umich.edu ''' 16165409Sgblack@eecs.umich.edu 16175429Sgblack@eecs.umich.edu class Rdm5reg(RdRegOp): 16185429Sgblack@eecs.umich.edu code = ''' 16195429Sgblack@eecs.umich.edu DestReg = M5Reg; 16205429Sgblack@eecs.umich.edu ''' 16215429Sgblack@eecs.umich.edu 16225294Sgblack@eecs.umich.edu class Wrdl(RegOp): 16235294Sgblack@eecs.umich.edu code = ''' 16245294Sgblack@eecs.umich.edu SegDescriptor desc = SrcReg1; 16255433Sgblack@eecs.umich.edu SegSelector selector = SrcReg2; 16268857Sgblack@eecs.umich.edu // This while loop is so we can use break statements in the code 16278857Sgblack@eecs.umich.edu // below to skip the rest of this section without a bunch of 16288857Sgblack@eecs.umich.edu // nesting. 16298857Sgblack@eecs.umich.edu while (true) { 16308857Sgblack@eecs.umich.edu if (selector.si || selector.ti) { 16318857Sgblack@eecs.umich.edu if (!desc.p) { 16328857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16338857Sgblack@eecs.umich.edu "Segment not present.\\n"); 16348857Sgblack@eecs.umich.edu break; 16355901Sgblack@eecs.umich.edu } 16368857Sgblack@eecs.umich.edu SegAttr attr = 0; 16378857Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 16388857Sgblack@eecs.umich.edu attr.unusable = 0; 16398857Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 16408857Sgblack@eecs.umich.edu attr.longMode = desc.l; 16418857Sgblack@eecs.umich.edu attr.avl = desc.avl; 16428857Sgblack@eecs.umich.edu attr.granularity = desc.g; 16438857Sgblack@eecs.umich.edu attr.present = desc.p; 16448857Sgblack@eecs.umich.edu attr.system = desc.s; 16458857Sgblack@eecs.umich.edu attr.type = desc.type; 16468857Sgblack@eecs.umich.edu if (!desc.s) { 16478857Sgblack@eecs.umich.edu // The expand down bit happens to be set for gates. 16488857Sgblack@eecs.umich.edu if (desc.type.e) { 16498857Sgblack@eecs.umich.edu fault = new GenericISA::M5PanicFault( 16508857Sgblack@eecs.umich.edu "Gate descriptor encountered.\\n"); 16518857Sgblack@eecs.umich.edu break; 16528857Sgblack@eecs.umich.edu } 16538857Sgblack@eecs.umich.edu attr.readable = 1; 16548857Sgblack@eecs.umich.edu attr.writable = 1; 16558857Sgblack@eecs.umich.edu attr.expandDown = 0; 16568857Sgblack@eecs.umich.edu } else { 16578857Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 16588857Sgblack@eecs.umich.edu attr.expandDown = 0; 16598857Sgblack@eecs.umich.edu attr.readable = desc.type.r; 16608857Sgblack@eecs.umich.edu attr.writable = 0; 16618857Sgblack@eecs.umich.edu } else { 16628857Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 16638857Sgblack@eecs.umich.edu attr.readable = 1; 16648857Sgblack@eecs.umich.edu attr.writable = desc.type.w; 16658857Sgblack@eecs.umich.edu } 16668857Sgblack@eecs.umich.edu } 16678857Sgblack@eecs.umich.edu Addr base = desc.baseLow | (desc.baseHigh << 24); 16688857Sgblack@eecs.umich.edu Addr limit = desc.limitLow | (desc.limitHigh << 16); 16698857Sgblack@eecs.umich.edu if (desc.g) 16708857Sgblack@eecs.umich.edu limit = (limit << 12) | mask(12); 16718857Sgblack@eecs.umich.edu SegBaseDest = base; 16728857Sgblack@eecs.umich.edu SegLimitDest = limit; 16738857Sgblack@eecs.umich.edu SegAttrDest = attr; 16745433Sgblack@eecs.umich.edu } else { 16758857Sgblack@eecs.umich.edu SegBaseDest = SegBaseDest; 16768857Sgblack@eecs.umich.edu SegLimitDest = SegLimitDest; 16778857Sgblack@eecs.umich.edu SegAttrDest = SegAttrDest; 16785433Sgblack@eecs.umich.edu } 16798857Sgblack@eecs.umich.edu break; 16805294Sgblack@eecs.umich.edu } 16815290Sgblack@eecs.umich.edu ''' 16829896Sandreas@sandberg.pp.se 16839896Sandreas@sandberg.pp.se class Wrxftw(WrRegOp): 16849896Sandreas@sandberg.pp.se def __init__(self, src1, **kwargs): 16859896Sandreas@sandberg.pp.se super(Wrxftw, self).__init__(src1, "InstRegIndex(NUM_INTREGS)", \ 16869896Sandreas@sandberg.pp.se **kwargs) 16879896Sandreas@sandberg.pp.se 16889896Sandreas@sandberg.pp.se code = ''' 16899896Sandreas@sandberg.pp.se FTW = X86ISA::convX87XTagsToTags(SrcReg1); 16909896Sandreas@sandberg.pp.se ''' 16919896Sandreas@sandberg.pp.se 16929896Sandreas@sandberg.pp.se class Rdxftw(RdRegOp): 16939896Sandreas@sandberg.pp.se code = ''' 16949896Sandreas@sandberg.pp.se DestReg = X86ISA::convX87TagsToXTags(FTW); 16959896Sandreas@sandberg.pp.se ''' 16964519Sgblack@eecs.umich.edu}}; 1697