ldstop.isa revision 10184:bbfa3152bdea
12381SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 22381SN/A// All rights reserved. 32381SN/A// 42381SN/A// The license below extends only to copyright in the software and shall 52381SN/A// not be construed as granting a license to any other intellectual 62381SN/A// property including but not limited to intellectual property relating 72381SN/A// to a hardware implementation of the functionality of the software 82381SN/A// licensed hereunder. You may use the software subject to the license 92381SN/A// terms below provided that you ensure that this notice is replicated 102381SN/A// unmodified and in its entirety in all distributions of the software, 112381SN/A// modified or unmodified, in source code or in binary form. 122381SN/A// 132381SN/A// Copyright (c) 2008 The Regents of The University of Michigan 142381SN/A// All rights reserved. 152381SN/A// 162381SN/A// Redistribution and use in source and binary forms, with or without 172381SN/A// modification, are permitted provided that the following conditions are 182381SN/A// met: redistributions of source code must retain the above copyright 192381SN/A// notice, this list of conditions and the following disclaimer; 202381SN/A// redistributions in binary form must reproduce the above copyright 212381SN/A// notice, this list of conditions and the following disclaimer in the 222381SN/A// documentation and/or other materials provided with the distribution; 232381SN/A// neither the name of the copyright holders nor the names of its 242381SN/A// contributors may be used to endorse or promote products derived from 252381SN/A// this software without specific prior written permission. 262381SN/A// 272381SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282381SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292381SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302381SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312381SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322381SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332381SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342381SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352381SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362381SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372381SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382381SN/A// 392381SN/A// Authors: Gabe Black 402381SN/A 412381SN/A////////////////////////////////////////////////////////////////////////// 422381SN/A// 432381SN/A// LdStOp Microop templates 442439SN/A// 452381SN/A////////////////////////////////////////////////////////////////////////// 462381SN/A 472381SN/A// LEA template 482381SN/A 492407SN/Adef template MicroLeaExecute {{ 502407SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 512407SN/A Trace::InstRecord *traceData) const 522407SN/A { 532407SN/A Fault fault = NoFault; 542407SN/A Addr EA; 552407SN/A 562407SN/A %(op_decl)s; 572521SN/A %(op_rd)s; 582407SN/A %(ea_code)s; 592381SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 602381SN/A 612381SN/A %(code)s; 622381SN/A if(fault == NoFault) 632381SN/A { 642381SN/A %(op_wb)s; 652381SN/A } 662381SN/A 672381SN/A return fault; 682381SN/A } 692381SN/A}}; 702381SN/A 712381SN/Adef template MicroLeaDeclare {{ 722640Sstever@eecs.umich.edu class %(class_name)s : public %(base_class)s 732640Sstever@eecs.umich.edu { 742640Sstever@eecs.umich.edu public: 752640Sstever@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 762640Sstever@eecs.umich.edu const char * instMnem, uint64_t setFlags, 772661Sstever@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 782661Sstever@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 792661Sstever@eecs.umich.edu InstRegIndex _data, 802661Sstever@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 812661Sstever@eecs.umich.edu Request::FlagsType _memFlags); 822381SN/A 832381SN/A %(BasicExecDeclare)s 842640Sstever@eecs.umich.edu }; 852640Sstever@eecs.umich.edu}}; 862640Sstever@eecs.umich.edu 872640Sstever@eecs.umich.edu// Load templates 882640Sstever@eecs.umich.edu 892640Sstever@eecs.umich.edudef template MicroLoadExecute {{ 902640Sstever@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 912661Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 922640Sstever@eecs.umich.edu { 932640Sstever@eecs.umich.edu Fault fault = NoFault; 942640Sstever@eecs.umich.edu Addr EA; 952640Sstever@eecs.umich.edu 962640Sstever@eecs.umich.edu %(op_decl)s; 972474SN/A %(op_rd)s; 982640Sstever@eecs.umich.edu %(ea_code)s; 992381SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1002657Ssaidi@eecs.umich.edu 1012657Ssaidi@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags); 1022381SN/A 1032381SN/A if (fault == NoFault) { 1042381SN/A %(code)s; 1052381SN/A } else if (memFlags & Request::PREFETCH) { 1062381SN/A // For prefetches, ignore any faults/exceptions. 1072381SN/A return NoFault; 1082381SN/A } 1092642Sstever@eecs.umich.edu if(fault == NoFault) 1102381SN/A { 1112642Sstever@eecs.umich.edu %(op_wb)s; 1122408SN/A } 1132408SN/A 1142409SN/A return fault; 1152408SN/A } 1162381SN/A}}; 1172381SN/A 1182406SN/Adef template MicroLoadInitiateAcc {{ 1192406SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1202406SN/A Trace::InstRecord * traceData) const 1212381SN/A { 1222630SN/A Fault fault = NoFault; 1232381SN/A Addr EA; 1242381SN/A 1252630SN/A %(op_decl)s; 1262381SN/A %(op_rd)s; 1272381SN/A %(ea_code)s; 1282630SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1292381SN/A 1302381SN/A fault = readMemTiming(xc, traceData, EA, Mem, dataSize, memFlags); 1312381SN/A 1322381SN/A return fault; 1332381SN/A } 1342381SN/A}}; 1352381SN/A 1362381SN/Adef template MicroLoadCompleteAcc {{ 1372657Ssaidi@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1382381SN/A %(CPU_exec_context)s * xc, 1392381SN/A Trace::InstRecord * traceData) const 1402381SN/A { 1412381SN/A Fault fault = NoFault; 1422381SN/A 1432381SN/A %(op_decl)s; 1442406SN/A %(op_rd)s; 1452381SN/A 1462381SN/A Mem = getMem(pkt, dataSize, traceData); 1472381SN/A 1482521SN/A %(code)s; 1492521SN/A 1502381SN/A if(fault == NoFault) 1512521SN/A { 1522521SN/A %(op_wb)s; 1532407SN/A } 1542381SN/A 1552381SN/A return fault; 1562381SN/A } 1572381SN/A}}; 1582381SN/A 1592381SN/A// Store templates 1602381SN/A 1612381SN/Adef template MicroStoreExecute {{ 1622657Ssaidi@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, 1632381SN/A Trace::InstRecord *traceData) const 1642381SN/A { 1652381SN/A Fault fault = NoFault; 1662630SN/A 1672381SN/A Addr EA; 1682381SN/A %(op_decl)s; 1692381SN/A %(op_rd)s; 1702381SN/A %(ea_code)s; 1712381SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1722630SN/A 1732381SN/A %(code)s; 1742381SN/A 1752381SN/A if(fault == NoFault) 1762381SN/A { 1772520SN/A fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA, 1782520SN/A memFlags, NULL); 1792381SN/A if(fault == NoFault) 1802630SN/A { 1812381SN/A %(op_wb)s; 1822381SN/A } 1832381SN/A } 1842381SN/A 1852381SN/A return fault; 1862381SN/A } 1872381SN/A}}; 1882381SN/A 1892381SN/Adef template MicroStoreInitiateAcc {{ 1902381SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1912657Ssaidi@eecs.umich.edu Trace::InstRecord * traceData) const 1922381SN/A { 1932381SN/A Fault fault = NoFault; 1942381SN/A 1952381SN/A Addr EA; 1962406SN/A %(op_decl)s; 1972381SN/A %(op_rd)s; 1982381SN/A %(ea_code)s; 1992381SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 2002381SN/A 2012521SN/A %(code)s; 2022521SN/A 2032381SN/A if(fault == NoFault) 2042461SN/A { 2052461SN/A fault = writeMemTiming(xc, traceData, Mem, dataSize, EA, 2062461SN/A memFlags, NULL); 2072461SN/A } 2082461SN/A return fault; 2092519SN/A } 2102381SN/A}}; 2112381SN/A 2122381SN/Adef template MicroStoreCompleteAcc {{ 2132381SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 2142381SN/A %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const 2152381SN/A { 2162519SN/A %(op_decl)s; 2172381SN/A %(op_rd)s; 2182381SN/A %(complete_code)s; 2192381SN/A %(op_wb)s; 2202461SN/A return NoFault; 2212381SN/A } 2222381SN/A}}; 2232519SN/A 2242405SN/A// Common templates 2252405SN/A 2262405SN/A//This delcares the initiateAcc function in memory operations 2272405SN/Adef template InitiateAccDeclare {{ 2282405SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 2292641Sstever@eecs.umich.edu}}; 2302381SN/A 2312381SN/A//This declares the completeAcc function in memory operations 2322520SN/Adef template CompleteAccDeclare {{ 2332520SN/A Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 2342520SN/A}}; 2352520SN/A 2362520SN/Adef template MicroLdStOpDeclare {{ 2372520SN/A class %(class_name)s : public %(base_class)s 2382520SN/A { 2392520SN/A public: 2402640Sstever@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 2412640Sstever@eecs.umich.edu const char * instMnem, uint64_t setFlags, 2422640Sstever@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2432640Sstever@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 2442630SN/A InstRegIndex _data, 2452630SN/A uint8_t _dataSize, uint8_t _addressSize, 2462630SN/A Request::FlagsType _memFlags); 2472590SN/A 2482521SN/A %(BasicExecDeclare)s 2492521SN/A 2502521SN/A %(InitiateAccDeclare)s 2512521SN/A 2522521SN/A %(CompleteAccDeclare)s 2532521SN/A }; 2542521SN/A}}; 2552521SN/A 2562521SN/Adef template MicroLdStOpConstructor {{ 2572521SN/A %(class_name)s::%(class_name)s( 2582521SN/A ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 2592521SN/A uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2602521SN/A uint64_t _disp, InstRegIndex _segment, 2612521SN/A InstRegIndex _data, 2622520SN/A uint8_t _dataSize, uint8_t _addressSize, 2632520SN/A Request::FlagsType _memFlags) : 2642381SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 265 _scale, _index, _base, 266 _disp, _segment, _data, 267 _dataSize, _addressSize, _memFlags, %(op_class)s) 268 { 269 %(constructor)s; 270 } 271}}; 272 273let {{ 274 class LdStOp(X86Microop): 275 def __init__(self, data, segment, addr, disp, 276 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): 277 self.data = data 278 [self.scale, self.index, self.base] = addr 279 self.disp = disp 280 self.segment = segment 281 self.dataSize = dataSize 282 self.addressSize = addressSize 283 self.memFlags = baseFlags 284 if atCPL0: 285 self.memFlags += " | (CPL0FlagBit << FlagShift)" 286 self.instFlags = "" 287 if prefetch: 288 self.memFlags += " | Request::PREFETCH" 289 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 290 if nonSpec: 291 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" 292 self.memFlags += " | (machInst.legacy.addr ? " + \ 293 "(AddrSizeFlagBit << FlagShift) : 0)" 294 295 def getAllocator(self, microFlags): 296 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 297 %(flags)s, %(scale)s, %(index)s, %(base)s, 298 %(disp)s, %(segment)s, %(data)s, 299 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 300 "class_name" : self.className, 301 "flags" : self.microFlagsText(microFlags) + self.instFlags, 302 "scale" : self.scale, "index" : self.index, 303 "base" : self.base, 304 "disp" : self.disp, 305 "segment" : self.segment, "data" : self.data, 306 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 307 "memFlags" : self.memFlags} 308 return allocator 309 310 class BigLdStOp(X86Microop): 311 def __init__(self, data, segment, addr, disp, 312 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): 313 self.data = data 314 [self.scale, self.index, self.base] = addr 315 self.disp = disp 316 self.segment = segment 317 self.dataSize = dataSize 318 self.addressSize = addressSize 319 self.memFlags = baseFlags 320 if atCPL0: 321 self.memFlags += " | (CPL0FlagBit << FlagShift)" 322 self.instFlags = "" 323 if prefetch: 324 self.memFlags += " | Request::PREFETCH" 325 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 326 if nonSpec: 327 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" 328 self.memFlags += " | (machInst.legacy.addr ? " + \ 329 "(AddrSizeFlagBit << FlagShift) : 0)" 330 331 def getAllocator(self, microFlags): 332 allocString = ''' 333 (%(dataSize)s >= 4) ? 334 (StaticInstPtr)(new %(class_name)sBig(machInst, 335 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 336 %(base)s, %(disp)s, %(segment)s, %(data)s, 337 %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 338 (StaticInstPtr)(new %(class_name)s(machInst, 339 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 340 %(base)s, %(disp)s, %(segment)s, %(data)s, 341 %(dataSize)s, %(addressSize)s, %(memFlags)s)) 342 ''' 343 allocator = allocString % { 344 "class_name" : self.className, 345 "flags" : self.microFlagsText(microFlags) + self.instFlags, 346 "scale" : self.scale, "index" : self.index, 347 "base" : self.base, 348 "disp" : self.disp, 349 "segment" : self.segment, "data" : self.data, 350 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 351 "memFlags" : self.memFlags} 352 return allocator 353}}; 354 355let {{ 356 357 # Make these empty strings so that concatenating onto 358 # them will always work. 359 header_output = "" 360 decoder_output = "" 361 exec_output = "" 362 363 calculateEA = ''' 364 EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 365 ''' 366 367 def defineMicroLoadOp(mnemonic, code, bigCode='', 368 mem_flags="0", big=True): 369 global header_output 370 global decoder_output 371 global exec_output 372 global microopClasses 373 Name = mnemonic 374 name = mnemonic.lower() 375 376 # Build up the all register version of this micro op 377 iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', 378 {"code": code, "ea_code": calculateEA})] 379 if big: 380 iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', 381 {"code": bigCode, "ea_code": calculateEA})] 382 for iop in iops: 383 header_output += MicroLdStOpDeclare.subst(iop) 384 decoder_output += MicroLdStOpConstructor.subst(iop) 385 exec_output += MicroLoadExecute.subst(iop) 386 exec_output += MicroLoadInitiateAcc.subst(iop) 387 exec_output += MicroLoadCompleteAcc.subst(iop) 388 389 base = LdStOp 390 if big: 391 base = BigLdStOp 392 class LoadOp(base): 393 def __init__(self, data, segment, addr, disp = 0, 394 dataSize="env.dataSize", 395 addressSize="env.addressSize", 396 atCPL0=False, prefetch=False, nonSpec=False): 397 super(LoadOp, self).__init__(data, segment, addr, 398 disp, dataSize, addressSize, mem_flags, 399 atCPL0, prefetch, nonSpec) 400 self.className = Name 401 self.mnemonic = name 402 403 microopClasses[name] = LoadOp 404 405 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 406 'Data = Mem & mask(dataSize * 8);') 407 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 408 'Data = Mem & mask(dataSize * 8);', 409 '(StoreCheck << FlagShift)') 410 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 411 'Data = Mem & mask(dataSize * 8);', 412 '(StoreCheck << FlagShift) | Request::LOCKED') 413 414 defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False) 415 416 defineMicroLoadOp('Ldfp87', code=''' 417 switch (dataSize) 418 { 419 case 4: 420 FpData_df = *(float *)&Mem; 421 break; 422 case 8: 423 FpData_df = *(double *)&Mem; 424 break; 425 default: 426 panic("Unhandled data size in LdFp87.\\n"); 427 } 428 ''', big = False) 429 430 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"): 431 global header_output 432 global decoder_output 433 global exec_output 434 global microopClasses 435 Name = mnemonic 436 name = mnemonic.lower() 437 438 # Build up the all register version of this micro op 439 iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 440 {"code": code, 441 "complete_code": completeCode, 442 "ea_code": calculateEA}) 443 header_output += MicroLdStOpDeclare.subst(iop) 444 decoder_output += MicroLdStOpConstructor.subst(iop) 445 exec_output += MicroStoreExecute.subst(iop) 446 exec_output += MicroStoreInitiateAcc.subst(iop) 447 exec_output += MicroStoreCompleteAcc.subst(iop) 448 449 class StoreOp(LdStOp): 450 def __init__(self, data, segment, addr, disp = 0, 451 dataSize="env.dataSize", 452 addressSize="env.addressSize", 453 atCPL0=False, nonSpec=False): 454 super(StoreOp, self).__init__(data, segment, addr, disp, 455 dataSize, addressSize, mem_flags, atCPL0, False, 456 nonSpec) 457 self.className = Name 458 self.mnemonic = name 459 460 microopClasses[name] = StoreOp 461 462 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 463 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 464 mem_flags="Request::LOCKED") 465 466 defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;') 467 468 defineMicroStoreOp('Stfp87', code=''' 469 switch (dataSize) 470 { 471 case 4: { 472 float single(FpData_df); 473 Mem = *(uint32_t *)&single; 474 } break; 475 case 8: 476 Mem = *(uint64_t *)&FpData_df; 477 break; 478 default: 479 panic("Unhandled data size in StFp87.\\n"); 480 } 481 ''') 482 483 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 484 485 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 486 {"code": "Data = merge(Data, EA, dataSize);", 487 "ea_code": ''' 488 EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 489 '''}) 490 header_output += MicroLeaDeclare.subst(iop) 491 decoder_output += MicroLdStOpConstructor.subst(iop) 492 exec_output += MicroLeaExecute.subst(iop) 493 494 class LeaOp(LdStOp): 495 def __init__(self, data, segment, addr, disp = 0, 496 dataSize="env.dataSize", addressSize="env.addressSize"): 497 super(LeaOp, self).__init__(data, segment, addr, disp, 498 dataSize, addressSize, "0", False, False, False) 499 self.className = "Lea" 500 self.mnemonic = "lea" 501 502 microopClasses["lea"] = LeaOp 503 504 505 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 506 {"code": "xc->demapPage(EA, 0);", 507 "ea_code": calculateEA}) 508 header_output += MicroLeaDeclare.subst(iop) 509 decoder_output += MicroLdStOpConstructor.subst(iop) 510 exec_output += MicroLeaExecute.subst(iop) 511 512 class TiaOp(LdStOp): 513 def __init__(self, segment, addr, disp = 0, 514 dataSize="env.dataSize", 515 addressSize="env.addressSize"): 516 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 517 addr, disp, dataSize, addressSize, "0", False, False, 518 False) 519 self.className = "Tia" 520 self.mnemonic = "tia" 521 522 microopClasses["tia"] = TiaOp 523 524 class CdaOp(LdStOp): 525 def __init__(self, segment, addr, disp = 0, 526 dataSize="env.dataSize", 527 addressSize="env.addressSize", atCPL0=False): 528 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 529 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 530 atCPL0, False, False) 531 self.className = "Cda" 532 self.mnemonic = "cda" 533 534 microopClasses["cda"] = CdaOp 535}}; 536 537