base.isa revision 4534
110515SN/A// -*- mode:c++ -*-
210515SN/A
310515SN/A// Copyright (c) 2007 The Hewlett-Packard Development Company
410515SN/A// All rights reserved.
510515SN/A//
610515SN/A// Redistribution and use of this software in source and binary forms,
710515SN/A// with or without modification, are permitted provided that the
810515SN/A// following conditions are met:
910515SN/A//
1010515SN/A// The software must be used only for Non-Commercial Use which means any
1110515SN/A// use which is NOT directed to receiving any direct monetary
1210515SN/A// compensation for, or commercial advantage from such use.  Illustrative
1310515SN/A// examples of non-commercial use are academic research, personal study,
1410515SN/A// teaching, education and corporate research & development.
1511570SCurtis.Dunham@arm.com// Illustrative examples of commercial use are distributing products for
1610515SN/A// commercial advantage and providing services using the software for
1710515SN/A// commercial advantage.
1810515SN/A//
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2011570SCurtis.Dunham@arm.com// covered by patents for commercial use, please contact:
2110515SN/A//     Director of Intellectual Property Licensing
2210515SN/A//     Office of Strategy and Technology
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2610515SN/A//
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3410515SN/A// this software without specific prior written permission.  No right of
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4110736SN/A// notice to acknowledge the contribution from this software where
4210515SN/A// applicable, this list of conditions and the disclaimer below.
4311167Sjthestness@gmail.com//
4410515SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
4511570SCurtis.Dunham@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
4611570SCurtis.Dunham@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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5410515SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5511570SCurtis.Dunham@arm.com//
5611570SCurtis.Dunham@arm.com// Authors: Gabe Black
5710515SN/A
5810515SN/Alet {{
5910515SN/A    # This will be populated with mappings between microop mnemonics and
6010515SN/A    # the classes that represent them.
6110515SN/A    microopClasses = {}
6210515SN/A}};
6310515SN/A
6410515SN/A//A class which is the base of all x86 micro ops. It provides a function to
6510515SN/A//set necessary flags appropriately.
6610515SN/Aoutput header {{
6710515SN/A    class X86MicroOpBase : public X86StaticInst
6810515SN/A    {
6911570SCurtis.Dunham@arm.com      protected:
7010515SN/A        const char * instMnem;
7110515SN/A        uint8_t opSize;
7211570SCurtis.Dunham@arm.com        uint8_t addrSize;
7311570SCurtis.Dunham@arm.com
7411570SCurtis.Dunham@arm.com        X86MicroOpBase(ExtMachInst _machInst,
7511570SCurtis.Dunham@arm.com                const char *mnem, const char *_instMnem,
7610515SN/A                bool isMicro, bool isDelayed,
7710515SN/A                bool isFirst, bool isLast,
7810515SN/A                OpClass __opClass) :
7910515SN/A            X86StaticInst(mnem, _machInst, __opClass),
8010515SN/A            instMnem(_instMnem)
8110515SN/A        {
8210515SN/A            flags[IsMicroOp] = isMicro;
8310515SN/A            flags[IsDelayedCommit] = isDelayed;
8410515SN/A            flags[IsFirstMicroOp] = isFirst;
8510515SN/A            flags[IsLastMicroOp] = isLast;
8610515SN/A        }
8710515SN/A
8810515SN/A        std::string generateDisassembly(Addr pc,
8910515SN/A                const SymbolTable *symtab) const
9010515SN/A        {
9110515SN/A            std::stringstream ss;
9210515SN/A
9310515SN/A            ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
9410515SN/A
9510515SN/A            return ss.str();
9610515SN/A        }
9710515SN/A    };
9810515SN/A}};
9910515SN/A
10010515SN/A//////////////////////////////////////////////////////////////////////////
10110515SN/A//
10211570SCurtis.Dunham@arm.com// Base class for the python representation of x86 microops
10310515SN/A//
10410515SN/A//////////////////////////////////////////////////////////////////////////
10510515SN/A
10610515SN/Alet {{
10710515SN/A    class X86Microop(object):
10810515SN/A        def __init__(self, name):
10910515SN/A            self.name = name
11010515SN/A
11110515SN/A        # This converts a list of python bools into
11210515SN/A        # a comma seperated list of C++ bools.
11310515SN/A        def microFlagsText(self, vals):
11410515SN/A            text = ""
11510515SN/A            for val in vals:
11610515SN/A                if val:
11710515SN/A                    text += ", true"
11810515SN/A                else:
11910515SN/A                    text += ", false"
12011570SCurtis.Dunham@arm.com            return text
12110515SN/A
12210515SN/A        def getAllocator(self, mnemonic, *microFlags):
12310515SN/A            return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags))
12410515SN/A}};
12510515SN/A
12610515SN/A//////////////////////////////////////////////////////////////////////////
12710515SN/A//
12810515SN/A// LdStOp Microop templates
12910515SN/A//
13010515SN/A//////////////////////////////////////////////////////////////////////////
13110515SN/A
13210515SN/Adef template MicroLdStOpDeclare {{
13310515SN/A    class %(class_name)s : public X86MicroOpBase
13410515SN/A    {
13510515SN/A      protected:
13610515SN/A        const uint8_t scale;
13710515SN/A        const RegIndex index;
13810515SN/A        const RegIndex base;
13911570SCurtis.Dunham@arm.com        const uint64_t disp;
14011570SCurtis.Dunham@arm.com        const uint8_t segment;
14111570SCurtis.Dunham@arm.com        const RegIndex data;
14211570SCurtis.Dunham@arm.com        const uint8_t dataSize;
14310515SN/A        const uint8_t addressSize;
14410515SN/A        void buildMe();
14510515SN/A
14610515SN/A      public:
14710515SN/A        %(class_name)s(ExtMachInst _machInst,
14810515SN/A                const char * instMnem,
14910515SN/A                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
15010515SN/A                uint8_t _scale, RegIndex _index, RegIndex _base,
15110515SN/A                uint64_t _disp, uint8_t _segment,
15210515SN/A                RegIndex _data,
15310515SN/A                uint8_t _dataSize, uint8_t _addressSize);
15410515SN/A
15510515SN/A        %(class_name)s(ExtMachInst _machInst,
15610515SN/A                const char * instMnem,
15710515SN/A                uint8_t _scale, RegIndex _index, RegIndex _base,
15811103Snilay@cs.wisc.edu                uint64_t _disp, uint8_t _segment,
15910515SN/A                RegIndex _data,
16010515SN/A                uint8_t _dataSize, uint8_t _addressSize);
16110515SN/A
16210515SN/A        %(BasicExecDeclare)s
16311239Sandreas.sandberg@arm.com    };
16411570SCurtis.Dunham@arm.com}};
16510636SN/A
16610515SN/Adef template MicroLdStOpConstructor {{
16710515SN/A
16810900Snilay@cs.wisc.edu    inline void %(class_name)s::buildMe()
16910515SN/A    {
17010515SN/A        %(constructor)s;
17111570SCurtis.Dunham@arm.com    }
17211570SCurtis.Dunham@arm.com
17311570SCurtis.Dunham@arm.com    inline %(class_name)s::%(class_name)s(
17411570SCurtis.Dunham@arm.com            ExtMachInst machInst, const char * instMnem,
17510515SN/A            uint8_t _scale, RegIndex _index, RegIndex _base,
17610515SN/A            uint64_t _disp, uint8_t _segment,
17710515SN/A            RegIndex _data,
17810515SN/A            uint8_t _dataSize, uint8_t _addressSize) :
17910515SN/A        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
18010515SN/A                false, false, false, false, %(op_class)s),
18110515SN/A                scale(_scale), index(_index), base(_base),
18210515SN/A                disp(_disp), segment(_segment),
18310515SN/A                data(_data),
18411239Sandreas.sandberg@arm.com                dataSize(_dataSize), addressSize(_addressSize)
18510515SN/A    {
18610515SN/A        buildMe();
18710515SN/A    }
18810515SN/A
18910515SN/A    inline %(class_name)s::%(class_name)s(
19010515SN/A            ExtMachInst machInst, const char * instMnem,
19110515SN/A            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
19210515SN/A            uint8_t _scale, RegIndex _index, RegIndex _base,
19311570SCurtis.Dunham@arm.com            uint64_t _disp, uint8_t segment,
19410515SN/A            RegIndex data,
19510515SN/A            uint8_t dataSize, uint8_t addressSize) :
19611570SCurtis.Dunham@arm.com        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
19711570SCurtis.Dunham@arm.com                isMicro, isDelayed, isFirst, isLast, %(op_class)s),
19811570SCurtis.Dunham@arm.com                scale(_scale), index(_index), base(_base),
19911570SCurtis.Dunham@arm.com                disp(_disp), segment(_segment),
20010515SN/A                data(_data),
20110515SN/A                dataSize(_dataSize), addressSize(_addressSize)
20210515SN/A    {
20310515SN/A        buildMe();
20410515SN/A    }
20510515SN/A}};
20610515SN/A
20710515SN/A//////////////////////////////////////////////////////////////////////////
20810736SN/A//
20910515SN/A// FpOp Microop templates
21010515SN/A//
21110515SN/A//////////////////////////////////////////////////////////////////////////
21210515SN/A
21310515SN/A//TODO Actually write an fp microop base class.
21410515SN/A