microasm.isa revision 5676:cca6726c0d88 
1// -*- mode:c++ -*-
2
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56// Authors: Gabe Black
57
58//Include the definitions of the micro ops.
59//These are python representations of static insts which stand on their own
60//and make up an internal instruction set. They are used by the micro
61//assembler.
62##include "microops/microops.isa"
63
64//Include code to build macroops in both C++ and python.
65##include "macroop.isa"
66
67//Include code to fill out the microcode ROM in both C++ and python.
68##include "rom.isa"
69
70let {{
71    import sys
72    sys.path[0:0] = ["src/arch/x86/isa/"]
73    from insts import microcode
74    # print microcode
75    from micro_asm import MicroAssembler, Rom_Macroop
76    mainRom = X86MicrocodeRom('main ROM')
77    assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
78    # Add in symbols for the microcode registers
79    for num in range(15):
80        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
81    for num in range(7):
82        assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
83    # Add in symbols for the segment descriptor registers
84    for letter in ("C", "D", "E", "F", "G", "H", "S"):
85        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
86
87    # Add in symbols for the various checks of segment selectors.
88    for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck",
89                  "SSCheck", "IretCheck", "IntCSCheck"):
90        assembler.symbols[check] = "Seg%s" % check
91
92    for reg in ("TR", "IDTR"):
93        assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
94
95    for reg in ("TSL", "TSG"):
96        assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
97
98    # Miscellaneous symbols
99    symbols = {
100        "reg" : "env.reg",
101        "xmml" : "FLOATREG_XMM_LOW(env.reg)",
102        "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
103        "regm" : "env.regm",
104        "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
105        "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
106        "imm" : "adjustedImm",
107        "disp" : "adjustedDisp",
108        "seg" : "env.seg",
109        "scale" : "env.scale",
110        "index" : "env.index",
111        "base" : "env.base",
112        "dsz" : "env.dataSize",
113        "asz" : "env.addressSize",
114        "ssz" : "env.stackSize"
115    }
116    assembler.symbols.update(symbols)
117
118    assembler.symbols["ldsz"] = \
119        "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
120
121    assembler.symbols["lasz"] = \
122        "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
123
124    assembler.symbols["lssz"] = \
125        "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
126
127    # Short hand for common scale-index-base combinations.
128    assembler.symbols["sib"] = \
129        [symbols["scale"], symbols["index"], symbols["base"]]
130    assembler.symbols["riprel"] = \
131        ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
132
133    # This segment selects an internal address space mapped to MSRs,
134    # CPUID info, etc.
135    assembler.symbols["intseg"] = "SEGMENT_REG_MS"
136    # This segment always has base 0, and doesn't imply any special handling
137    # like the internal segment above
138    assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
139
140    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
141        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
142
143    for reg in range(15):
144        assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
145
146    for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
147                 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
148        assembler.symbols[flag] = flag + "Bit"
149
150    for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
151                 'MSTRZ', 'STRZ', 'MSTRC',
152                 'OF', 'CF', 'ZF', 'CvZF',
153                 'SF', 'PF', 'SxOF', 'SxOvZF'):
154        assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
155        assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
156    assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
157    assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
158
159    assembler.symbols["CTrue"] = "ConditionTests::True"
160    assembler.symbols["CFalse"] = "ConditionTests::False"
161
162    # Code literal which forces a default 64 bit operand size in 64 bit mode.
163    assembler.symbols["oszIn64Override"] = '''
164    if (machInst.mode.submode == SixtyFourBitMode &&
165            env.dataSize == 4)
166        env.dataSize = 8;
167    '''
168
169    assembler.symbols["oszForPseudoDesc"] = '''
170    if (machInst.mode.submode == SixtyFourBitMode)
171        env.dataSize = 8;
172    else
173        env.dataSize = 4;
174    '''
175
176    def trimImm(width):
177        return "adjustedImm = adjustedImm & mask(%s);" % width
178
179    assembler.symbols["trimImm"] = trimImm
180
181    def labeler(labelStr):
182        return "label_%s" % labelStr
183
184    assembler.symbols["label"] = labeler
185
186    def rom_labeler(labelStr):
187        return "romMicroPC(RomLabels::extern_label_%s)" % labelStr
188
189    assembler.symbols["rom_label"] = rom_labeler
190
191    def rom_local_labeler(labelStr):
192        return "romMicroPC(RomLabels::label_%s)" % labelStr
193
194    assembler.symbols["rom_local_label"] = rom_local_labeler
195
196    def stack_index(index):
197        return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
198
199    assembler.symbols["st"] = stack_index
200
201    macroopDict = assembler.assemble(microcode)
202
203    decoder_output += mainRom.getDefinition()
204    header_output += mainRom.getDeclaration()
205}};
206