microasm.isa revision 5426:0bdcc60ccc45 
1// -*- mode:c++ -*-
2
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56// Authors: Gabe Black
57
58//Include the definitions of the micro ops.
59//These are python representations of static insts which stand on their own
60//and make up an internal instruction set. They are used by the micro
61//assembler.
62##include "microops/microops.isa"
63
64//Include code to build macroops in both C++ and python.
65##include "macroop.isa"
66
67let {{
68    import sys
69    sys.path[0:0] = ["src/arch/x86/isa/"]
70    from insts import microcode
71    # print microcode
72    from micro_asm import MicroAssembler, Rom_Macroop, Rom
73    mainRom = Rom('main ROM')
74    assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
75    # Add in symbols for the microcode registers
76    for num in range(15):
77        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
78    for num in range(7):
79        assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
80    # Add in symbols for the segment descriptor registers
81    for letter in ("C", "D", "E", "F", "G", "S"):
82        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
83
84    for reg in ("TR", "IDTR"):
85        assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
86
87    for reg in ("TSL", "TSG"):
88        assembler.symbols[reg.lower()] = "SEGMENT_REG_%s" % reg
89
90    # Miscellaneous symbols
91    symbols = {
92        "reg" : "env.reg",
93        "xmml" : "FLOATREG_XMM_LOW(env.reg)",
94        "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
95        "regm" : "env.regm",
96        "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
97        "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
98        "imm" : "adjustedImm",
99        "disp" : "adjustedDisp",
100        "seg" : "env.seg",
101        "scale" : "env.scale",
102        "index" : "env.index",
103        "base" : "env.base",
104        "dsz" : "env.dataSize",
105        "asz" : "env.addressSize",
106        "ssz" : "env.stackSize"
107    }
108    assembler.symbols.update(symbols)
109
110    assembler.symbols["ldsz"] = \
111        "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)"
112
113    assembler.symbols["lasz"] = \
114        "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)"
115
116    assembler.symbols["lssz"] = \
117        "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)"
118
119    # Short hand for common scale-index-base combinations.
120    assembler.symbols["sib"] = \
121        [symbols["scale"], symbols["index"], symbols["base"]]
122    assembler.symbols["riprel"] = \
123        ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
124
125    # This segment selects an internal address space mapped to MSRs,
126    # CPUID info, etc.
127    assembler.symbols["intseg"] = "SEGMENT_REG_MS"
128    # This segment always has base 0, and doesn't imply any special handling
129    # like the internal segment above
130    assembler.symbols["flatseg"] = "SEGMENT_REG_LS"
131
132    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
133        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
134
135    for reg in range(15):
136        assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
137
138    for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \
139                 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'):
140        assembler.symbols[flag] = flag + "Bit"
141
142    for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
143                 'MSTRZ', 'STRZ', 'MSTRC',
144                 'OF', 'CF', 'ZF', 'CvZF',
145                 'SF', 'PF', 'SxOF', 'SxOvZF'):
146        assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
147        assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
148    assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
149    assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
150
151    assembler.symbols["CTrue"] = "ConditionTests::True"
152    assembler.symbols["CFalse"] = "ConditionTests::False"
153
154    # Code literal which forces a default 64 bit operand size in 64 bit mode.
155    assembler.symbols["oszIn64Override"] = '''
156    if (machInst.mode.submode == SixtyFourBitMode &&
157            env.dataSize == 4)
158        env.dataSize = 8;
159    '''
160
161    assembler.symbols["oszForPseudoDesc"] = '''
162    if (machInst.mode.submode == SixtyFourBitMode)
163        env.dataSize = 8;
164    else
165        env.dataSize = 4;
166    '''
167
168    def trimImm(width):
169        return "adjustedImm = adjustedImm & mask(%s);" % width
170
171    assembler.symbols["trimImm"] = trimImm
172
173    def labeler(labelStr):
174        return "label_%s" % labelStr
175
176    assembler.symbols["label"] = labeler
177
178    def stack_index(index):
179        return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
180
181    assembler.symbols["st"] = stack_index
182
183    macroopDict = assembler.assemble(microcode)
184}};
185