microasm.isa revision 4620:5acc50eeacf7 
1// -*- mode:c++ -*-
2
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56// Authors: Gabe Black
57
58//Include the definitions of the micro ops.
59//These are StaticInst classes which stand on their own and make up an
60//internal instruction set, and also python representations which are passed
61//into the microcode assembler.
62##include "microops/microops.isa"
63
64//Include code to build macroops in both C++ and python.
65##include "macroop.isa"
66
67let {{
68    import sys
69    sys.path[0:0] = ["src/arch/x86/isa/"]
70    from insts import microcode
71    # print microcode
72    from micro_asm import MicroAssembler, Rom_Macroop, Rom
73    mainRom = Rom('main ROM')
74    assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
75    # Add in symbols for the microcode registers
76    for num in range(15):
77        assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
78    # Add in symbols for the segment descriptor registers
79    for letter in ("C", "D", "E", "F", "G", "S"):
80        assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
81    # Miscellaneous symbols
82    symbols = {
83        "reg" : "env.reg",
84        "regm" : "env.regm",
85        "imm" : "IMMEDIATE",
86        "disp" : "DISPLACEMENT",
87        "scale" : "env.scale",
88        "index" : "env.index",
89        "base" : "env.base",
90        "dsz" : "env.dataSize",
91        "osz" : "env.operandSize",
92        "ssz" : "env.stackSize"
93    }
94
95    for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
96        assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
97    assembler.symbols.update(symbols)
98
99    # Code literal which forces a default 64 bit operand size in 64 bit mode.
100    assembler.symbols["oszIn64Override"] = '''
101    if (machInst.mode.submode == SixtyFourBitMode &&
102            env.dataSize == 4)
103        env.dataSize = 8;
104    '''
105
106    macroopDict = assembler.assemble(microcode)
107}};
108