control_registers.py revision 6345:f9ae7c3a036c
1# Copyright (c) 2009 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Gabe Black 28 29microcode = ''' 30def macroop CLTS { 31 rdcr t1, regIdx(0), dataSize=8 32 andi t1, t1, 0xF7, dataSize=1 33 wrcr regIdx(0), t1, dataSize=8 34}; 35 36def macroop LMSW_R { 37 rdcr t1, regIdx(0), dataSize=8 38 # This logic sets MP, EM, and TS to whatever is in the operand. It will 39 # set PE but not clear it. 40 limm t2, "~ULL(0xe)", dataSize=8 41 and t1, t1, t2, dataSize=8 42 andi t2, reg, 0xf, dataSize=8 43 or t1, t1, t2, dataSize=8 44 wrcr regIdx(0), t1, dataSize=8 45}; 46 47def macroop LMSW_M { 48 ld t3, seg, sib, disp, dataSize=2 49 rdcr t1, regIdx(0), dataSize=8 50 # This logic sets MP, EM, and TS to whatever is in the operand. It will 51 # set PE but not clear it. 52 limm t2, "~ULL(0xe)", dataSize=8 53 and t1, t1, t2, dataSize=8 54 andi t2, t3, 0xf, dataSize=8 55 or t1, t1, t2, dataSize=8 56 wrcr regIdx(0), t1, dataSize=8 57}; 58 59def macroop LMSW_P { 60 rdip t7, dataSize=asz 61 ld t3, seg, riprel, disp, dataSize=2 62 rdcr t1, regIdx(0), dataSize=8 63 # This logic sets MP, EM, and TS to whatever is in the operand. It will 64 # set PE but not clear it. 65 limm t2, "~ULL(0xe)", dataSize=8 66 and t1, t1, t2, dataSize=8 67 andi t2, t3, 0xf, dataSize=8 68 or t1, t1, t2, dataSize=8 69 wrcr regIdx(0), t1, dataSize=8 70}; 71 72def macroop SMSW_R { 73 rdcr reg, regIdx(0) 74}; 75 76def macroop SMSW_M { 77 rdcr t1, regIdx(0) 78 st t1, seg, sib, disp, dataSize=2 79}; 80 81def macroop SMSW_P { 82 rdcr t1, regIdx(0) 83 rdip t7, dataSize=asz 84 st t1, seg, riprel, disp, dataSize=2 85}; 86''' 87