romutil.py revision 5852 
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29microcode = '''
30def rom
31{
32    # This vectors the CPU into an interrupt handler in long mode.
33    # On entry, t1 is set to the vector of the interrupt and t7 is the current
34    # ip. We need that because rdip returns the next ip.
35    extern longModeInterrupt:
36
37    #
38    # Get the 64 bit interrupt or trap gate descriptor from the IDT
39    #
40
41    # Load the gate descriptor from the IDT
42    slli t4, t1, 4, dataSize=8
43    ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8
44    ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
45
46    # Check permissions
47    chks t1, t4, IntGateCheck
48
49    mov t1, t1, t4, dataSize=8
50
51    # Check that it's the right type
52    srli t4, t1, 40, dataSize=8
53    andi t4, t4, 0xe, dataSize=8
54    xori t4, t4, 0xe, flags=(EZF,), dataSize=8
55    fault "new GeneralProtection(0)", flags=(nCEZF,)
56
57
58    #
59    # Get the target CS descriptor using the selector in the gate
60    # descriptor.
61    #
62    srli t10, t4, 16, dataSize=8
63    andi t5, t10, 0xF8, dataSize=8
64    andi t0, t10, 0x4, flags=(EZF,), dataSize=2
65    br rom_local_label("globalDescriptor"), flags=(CEZF,)
66    ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
67    br rom_local_label("processDescriptor")
68globalDescriptor:
69    ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
70processDescriptor:
71    chks t10, t3, IntCSCheck, dataSize=8
72    wrdl hs, t3, t10, dataSize=8
73
74    # Stick the target offset in t9.
75    wrdh t9, t4, t2, dataSize=8
76
77
78    #
79    # Figure out where the stack should be
80    #
81
82    # Record what we might set the stack selector to.
83    rdsel t11, ss
84
85    # Check if we're changing privelege level. At this point we can assume
86    # we're going to a DPL that's less than or equal to the CPL.
87    rdattr t10, hs, dataSize=8
88    srli t10, t10, 3, dataSize=8
89    andi t10, t10, 3, dataSize=8
90    rdattr t5, cs, dataSize=8
91    srli t5, t5, 3, dataSize=8
92    sub t5, t5, t10, dataSize=8
93    andi t0, t5, 0x3, flags=(EZF,), dataSize=8
94    # We're going to change priviledge, so zero out the stack selector. We
95    # need to let the IST have priority so we don't branch yet.
96    wrsel t11, t0, flags=(nCEZF,)
97
98    # Check the IST field of the gate descriptor
99    srli t10, t4, 32, dataSize=8
100    andi t10, t10, 0x7, dataSize=8
101    subi t0, t10, 1, flags=(ECF,), dataSize=8
102    br rom_local_label("istStackSwitch"), flags=(nCECF,)
103    br rom_local_label("cplStackSwitch"), flags=(nCEZF,)
104
105    # If we're here, it's because the stack isn't being switched.
106    # Set t6 to the new rsp.
107    subi t6, rsp, 40, dataSize=8
108
109    # Align the stack
110    andi t6, t6, 0xF0, dataSize=1
111
112    # Check that we can access everything we need to on the stack
113    ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
114    ldst t0, hs, [1, t0, t6], 32, dataSize=8, addressSize=8
115    br rom_local_label("stackSwitched")
116
117istStackSwitch:
118    panic "IST based stack switching isn't implemented"
119    br rom_local_label("stackSwitched")
120
121cplStackSwitch:
122    panic "CPL change initiated stack switching isn't implemented"
123
124stackSwitched:
125
126
127    ##
128    ## Point of no return.
129    ## We're now going to irrevocably modify visible state.
130    ## Anything bad that's going to happen should have happened by now or will
131    ## happen right now.
132    ##
133    wrip t0, t9, dataSize=8
134
135
136    #
137    # Build up the interrupt stack frame
138    #
139
140
141    # Write out the contents of memory
142    st t7, hs, [1, t0, t6], dataSize=8
143    limm t5, 0, dataSize=8
144    rdsel t5, cs, dataSize=2
145    st t5, hs, [1, t0, t6], 8, dataSize=8
146    rflags t10, dataSize=8
147    st t10, hs, [1, t0, t6], 16, dataSize=8
148    st rsp, hs, [1, t0, t6], 24, dataSize=8
149    rdsel t5, ss, dataSize=2
150    st t5, hs, [1, t0, t6], 32, dataSize=8
151
152    # Set the stack segment
153    mov rsp, rsp, t6, dataSize=8
154    wrsel ss, t11, dataSize=2
155
156    #
157    # Set up the target code segment
158    #
159    srli t5, t4, 16, dataSize=8
160    andi t5, t5, 0xFF, dataSize=8
161    wrdl cs, t3, t5, dataSize=8
162    wrsel cs, t5, dataSize=2
163
164    #
165    # Adjust rflags which is still in t10 from above
166    #
167
168    # Set IF to the lowest bit of the original gate type.
169    # The type field of the original gate starts at bit 40.
170
171    # Set the TF, NT, and RF bits. We'll flip them at the end.
172    limm t6, (1 << 8) | (1 << 14) | (1 << 16)
173    or t10, t10, t6
174    srli t5, t4, 40, dataSize=8
175    srli t7, t10, 9, dataSize=8
176    xor t5, t7, t5, dataSize=8
177    andi t5, t5, 1, dataSize=8
178    slli t5, t5, 9, dataSize=8
179    or t6, t5, t6, dataSize=8
180
181    # Put the results into rflags
182    wrflags t6, t10
183
184    eret
185};
186
187def rom
188{
189    # This vectors the CPU into an interrupt handler in legacy mode.
190    extern legacyModeInterrupt:
191    panic "Legacy mode interrupts not implemented (in microcode)"
192    eret
193};
194'''
195