romutil.py revision 5903
15680Sgblack@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 25680Sgblack@eecs.umich.edu# All rights reserved. 35680Sgblack@eecs.umich.edu# 45680Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 55680Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 65680Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 75680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 85680Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 95680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 105680Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 115680Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 125680Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 135680Sgblack@eecs.umich.edu# this software without specific prior written permission. 145680Sgblack@eecs.umich.edu# 155680Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165680Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175680Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185680Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195680Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205680Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215680Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225680Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235680Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245680Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255680Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265680Sgblack@eecs.umich.edu# 275680Sgblack@eecs.umich.edu# Authors: Gabe Black 285680Sgblack@eecs.umich.edu 295856Sgblack@eecs.umich.eduintCodeTemplate = ''' 305680Sgblack@eecs.umich.edudef rom 315680Sgblack@eecs.umich.edu{ 325680Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in long mode. 335680Sgblack@eecs.umich.edu # On entry, t1 is set to the vector of the interrupt and t7 is the current 345680Sgblack@eecs.umich.edu # ip. We need that because rdip returns the next ip. 355856Sgblack@eecs.umich.edu extern %(startLabel)s: 365680Sgblack@eecs.umich.edu 375680Sgblack@eecs.umich.edu # 385680Sgblack@eecs.umich.edu # Get the 64 bit interrupt or trap gate descriptor from the IDT 395680Sgblack@eecs.umich.edu # 405680Sgblack@eecs.umich.edu 415680Sgblack@eecs.umich.edu # Load the gate descriptor from the IDT 425680Sgblack@eecs.umich.edu slli t4, t1, 4, dataSize=8 435680Sgblack@eecs.umich.edu ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8 445680Sgblack@eecs.umich.edu ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8 455680Sgblack@eecs.umich.edu 465853Sgblack@eecs.umich.edu # Make sure the descriptor is a legal gate. 475856Sgblack@eecs.umich.edu chks t1, t4, %(gateCheckType)s 485680Sgblack@eecs.umich.edu 495680Sgblack@eecs.umich.edu # 505680Sgblack@eecs.umich.edu # Get the target CS descriptor using the selector in the gate 515680Sgblack@eecs.umich.edu # descriptor. 525680Sgblack@eecs.umich.edu # 535852Sgblack@eecs.umich.edu srli t10, t4, 16, dataSize=8 545852Sgblack@eecs.umich.edu andi t5, t10, 0xF8, dataSize=8 555852Sgblack@eecs.umich.edu andi t0, t10, 0x4, flags=(EZF,), dataSize=2 565856Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,) 575680Sgblack@eecs.umich.edu ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8 585856Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_processDescriptor") 595856Sgblack@eecs.umich.edu%(startLabel)s_globalDescriptor: 605680Sgblack@eecs.umich.edu ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8 615856Sgblack@eecs.umich.edu%(startLabel)s_processDescriptor: 625852Sgblack@eecs.umich.edu chks t10, t3, IntCSCheck, dataSize=8 635852Sgblack@eecs.umich.edu wrdl hs, t3, t10, dataSize=8 645680Sgblack@eecs.umich.edu 655852Sgblack@eecs.umich.edu # Stick the target offset in t9. 665852Sgblack@eecs.umich.edu wrdh t9, t4, t2, dataSize=8 675680Sgblack@eecs.umich.edu 685680Sgblack@eecs.umich.edu 695680Sgblack@eecs.umich.edu # 705680Sgblack@eecs.umich.edu # Figure out where the stack should be 715680Sgblack@eecs.umich.edu # 725680Sgblack@eecs.umich.edu 735680Sgblack@eecs.umich.edu # Record what we might set the stack selector to. 745852Sgblack@eecs.umich.edu rdsel t11, ss 755680Sgblack@eecs.umich.edu 765680Sgblack@eecs.umich.edu # Check if we're changing privelege level. At this point we can assume 775680Sgblack@eecs.umich.edu # we're going to a DPL that's less than or equal to the CPL. 785852Sgblack@eecs.umich.edu rdattr t10, hs, dataSize=8 795852Sgblack@eecs.umich.edu srli t10, t10, 3, dataSize=8 805852Sgblack@eecs.umich.edu andi t10, t10, 3, dataSize=8 815680Sgblack@eecs.umich.edu rdattr t5, cs, dataSize=8 825680Sgblack@eecs.umich.edu srli t5, t5, 3, dataSize=8 835903Sgblack@eecs.umich.edu andi t5, t5, 0x3, dataSize=8 845903Sgblack@eecs.umich.edu sub t0, t5, t10, flags=(EZF,), dataSize=8 855680Sgblack@eecs.umich.edu # We're going to change priviledge, so zero out the stack selector. We 865680Sgblack@eecs.umich.edu # need to let the IST have priority so we don't branch yet. 875852Sgblack@eecs.umich.edu wrsel t11, t0, flags=(nCEZF,) 885680Sgblack@eecs.umich.edu 895680Sgblack@eecs.umich.edu # Check the IST field of the gate descriptor 905903Sgblack@eecs.umich.edu srli t12, t4, 32, dataSize=8 915903Sgblack@eecs.umich.edu andi t12, t12, 0x7, dataSize=8 925903Sgblack@eecs.umich.edu subi t0, t12, 1, flags=(ECF,), dataSize=8 935856Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,) 945856Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,) 955680Sgblack@eecs.umich.edu 965680Sgblack@eecs.umich.edu # If we're here, it's because the stack isn't being switched. 975856Sgblack@eecs.umich.edu # Set t6 to the new aligned rsp. 985858Sgblack@eecs.umich.edu mov t6, t6, rsp, dataSize=8 995903Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1005903Sgblack@eecs.umich.edu 1015903Sgblack@eecs.umich.edu%(startLabel)s_istStackSwitch: 1025903Sgblack@eecs.umich.edu panic "IST based stack switching isn't implemented" 1035903Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1045903Sgblack@eecs.umich.edu 1055903Sgblack@eecs.umich.edu%(startLabel)s_cplStackSwitch: 1065903Sgblack@eecs.umich.edu # Get the new rsp from the TSS 1075903Sgblack@eecs.umich.edu ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8 1085903Sgblack@eecs.umich.edu 1095903Sgblack@eecs.umich.edu%(startLabel)s_stackSwitched: 1105903Sgblack@eecs.umich.edu 1115680Sgblack@eecs.umich.edu andi t6, t6, 0xF0, dataSize=1 1125856Sgblack@eecs.umich.edu subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8 1135680Sgblack@eecs.umich.edu 1145680Sgblack@eecs.umich.edu # Check that we can access everything we need to on the stack 1155680Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8 1165856Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], \ 1175856Sgblack@eecs.umich.edu 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 1185680Sgblack@eecs.umich.edu 1195680Sgblack@eecs.umich.edu ## 1205680Sgblack@eecs.umich.edu ## Point of no return. 1215680Sgblack@eecs.umich.edu ## We're now going to irrevocably modify visible state. 1225852Sgblack@eecs.umich.edu ## Anything bad that's going to happen should have happened by now or will 1235852Sgblack@eecs.umich.edu ## happen right now. 1245680Sgblack@eecs.umich.edu ## 1255852Sgblack@eecs.umich.edu wrip t0, t9, dataSize=8 1265680Sgblack@eecs.umich.edu 1275680Sgblack@eecs.umich.edu 1285680Sgblack@eecs.umich.edu # 1295680Sgblack@eecs.umich.edu # Build up the interrupt stack frame 1305680Sgblack@eecs.umich.edu # 1315680Sgblack@eecs.umich.edu 1325852Sgblack@eecs.umich.edu 1335680Sgblack@eecs.umich.edu # Write out the contents of memory 1345856Sgblack@eecs.umich.edu %(errorCodeCode)s 1355856Sgblack@eecs.umich.edu st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 1365680Sgblack@eecs.umich.edu limm t5, 0, dataSize=8 1375680Sgblack@eecs.umich.edu rdsel t5, cs, dataSize=2 1385856Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8 1395852Sgblack@eecs.umich.edu rflags t10, dataSize=8 1405856Sgblack@eecs.umich.edu st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8 1415856Sgblack@eecs.umich.edu st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8 1425680Sgblack@eecs.umich.edu rdsel t5, ss, dataSize=2 1435856Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 1445680Sgblack@eecs.umich.edu 1455680Sgblack@eecs.umich.edu # Set the stack segment 1465680Sgblack@eecs.umich.edu mov rsp, rsp, t6, dataSize=8 1475852Sgblack@eecs.umich.edu wrsel ss, t11, dataSize=2 1485680Sgblack@eecs.umich.edu 1495680Sgblack@eecs.umich.edu # 1505680Sgblack@eecs.umich.edu # Set up the target code segment 1515680Sgblack@eecs.umich.edu # 1525852Sgblack@eecs.umich.edu srli t5, t4, 16, dataSize=8 1535680Sgblack@eecs.umich.edu andi t5, t5, 0xFF, dataSize=8 1545680Sgblack@eecs.umich.edu wrdl cs, t3, t5, dataSize=8 1555680Sgblack@eecs.umich.edu wrsel cs, t5, dataSize=2 1565680Sgblack@eecs.umich.edu 1575680Sgblack@eecs.umich.edu # 1585852Sgblack@eecs.umich.edu # Adjust rflags which is still in t10 from above 1595680Sgblack@eecs.umich.edu # 1605680Sgblack@eecs.umich.edu 1615680Sgblack@eecs.umich.edu # Set IF to the lowest bit of the original gate type. 1625680Sgblack@eecs.umich.edu # The type field of the original gate starts at bit 40. 1635680Sgblack@eecs.umich.edu 1645680Sgblack@eecs.umich.edu # Set the TF, NT, and RF bits. We'll flip them at the end. 1655680Sgblack@eecs.umich.edu limm t6, (1 << 8) | (1 << 14) | (1 << 16) 1665852Sgblack@eecs.umich.edu or t10, t10, t6 1675852Sgblack@eecs.umich.edu srli t5, t4, 40, dataSize=8 1685852Sgblack@eecs.umich.edu srli t7, t10, 9, dataSize=8 1695680Sgblack@eecs.umich.edu xor t5, t7, t5, dataSize=8 1705680Sgblack@eecs.umich.edu andi t5, t5, 1, dataSize=8 1715680Sgblack@eecs.umich.edu slli t5, t5, 9, dataSize=8 1725680Sgblack@eecs.umich.edu or t6, t5, t6, dataSize=8 1735680Sgblack@eecs.umich.edu 1745680Sgblack@eecs.umich.edu # Put the results into rflags 1755852Sgblack@eecs.umich.edu wrflags t6, t10 1765680Sgblack@eecs.umich.edu 1775680Sgblack@eecs.umich.edu eret 1785680Sgblack@eecs.umich.edu}; 1795856Sgblack@eecs.umich.edu''' 1805680Sgblack@eecs.umich.edu 1815856Sgblack@eecs.umich.edumicrocode = \ 1825856Sgblack@eecs.umich.eduintCodeTemplate % {\ 1835856Sgblack@eecs.umich.edu "startLabel" : "longModeInterrupt", 1845856Sgblack@eecs.umich.edu "gateCheckType" : "IntGateCheck", 1855856Sgblack@eecs.umich.edu "errorCodeSize" : 0, 1865856Sgblack@eecs.umich.edu "errorCodeCode" : "" 1875856Sgblack@eecs.umich.edu} + \ 1885856Sgblack@eecs.umich.eduintCodeTemplate % {\ 1895856Sgblack@eecs.umich.edu "startLabel" : "longModeSoftInterrupt", 1905856Sgblack@eecs.umich.edu "gateCheckType" : "SoftIntGateCheck", 1915856Sgblack@eecs.umich.edu "errorCodeSize" : 0, 1925856Sgblack@eecs.umich.edu "errorCodeCode" : "" 1935856Sgblack@eecs.umich.edu} + \ 1945856Sgblack@eecs.umich.eduintCodeTemplate % {\ 1955856Sgblack@eecs.umich.edu "startLabel" : "longModeInterruptWithError", 1965856Sgblack@eecs.umich.edu "gateCheckType" : "IntGateCheck", 1975856Sgblack@eecs.umich.edu "errorCodeSize" : 8, 1985856Sgblack@eecs.umich.edu "errorCodeCode" : ''' 1995856Sgblack@eecs.umich.edu st t15, hs, [1, t0, t6], dataSize=8, addressSize=8 2005856Sgblack@eecs.umich.edu ''' 2015856Sgblack@eecs.umich.edu} + \ 2025856Sgblack@eecs.umich.edu''' 2035680Sgblack@eecs.umich.edudef rom 2045680Sgblack@eecs.umich.edu{ 2055680Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in legacy mode. 2065680Sgblack@eecs.umich.edu extern legacyModeInterrupt: 2075680Sgblack@eecs.umich.edu panic "Legacy mode interrupts not implemented (in microcode)" 2085680Sgblack@eecs.umich.edu eret 2095680Sgblack@eecs.umich.edu}; 2105680Sgblack@eecs.umich.edu''' 211