romutil.py revision 5856
17119Sgblack@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 27119Sgblack@eecs.umich.edu# All rights reserved. 37120Sgblack@eecs.umich.edu# 47120Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57120Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 67120Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 77120Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 87120Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 97120Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 107120Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 117120Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 127120Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 137120Sgblack@eecs.umich.edu# this software without specific prior written permission. 147120Sgblack@eecs.umich.edu# 157119Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167119Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177119Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187119Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197119Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207119Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217119Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227119Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237119Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247119Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257119Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267119Sgblack@eecs.umich.edu# 277119Sgblack@eecs.umich.edu# Authors: Gabe Black 287119Sgblack@eecs.umich.edu 297119Sgblack@eecs.umich.eduintCodeTemplate = ''' 307119Sgblack@eecs.umich.edudef rom 317119Sgblack@eecs.umich.edu{ 327119Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in long mode. 337119Sgblack@eecs.umich.edu # On entry, t1 is set to the vector of the interrupt and t7 is the current 347119Sgblack@eecs.umich.edu # ip. We need that because rdip returns the next ip. 357119Sgblack@eecs.umich.edu extern %(startLabel)s: 367119Sgblack@eecs.umich.edu 377119Sgblack@eecs.umich.edu # 387119Sgblack@eecs.umich.edu # Get the 64 bit interrupt or trap gate descriptor from the IDT 397119Sgblack@eecs.umich.edu # 407119Sgblack@eecs.umich.edu 417119Sgblack@eecs.umich.edu # Load the gate descriptor from the IDT 427119Sgblack@eecs.umich.edu slli t4, t1, 4, dataSize=8 437119Sgblack@eecs.umich.edu ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8 447646Sgene.wu@arm.com ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8 457646Sgene.wu@arm.com 467646Sgene.wu@arm.com # Make sure the descriptor is a legal gate. 477646Sgene.wu@arm.com chks t1, t4, %(gateCheckType)s 487646Sgene.wu@arm.com 497646Sgene.wu@arm.com # 507646Sgene.wu@arm.com # Get the target CS descriptor using the selector in the gate 517646Sgene.wu@arm.com # descriptor. 527646Sgene.wu@arm.com # 537646Sgene.wu@arm.com srli t10, t4, 16, dataSize=8 547646Sgene.wu@arm.com andi t5, t10, 0xF8, dataSize=8 557646Sgene.wu@arm.com andi t0, t10, 0x4, flags=(EZF,), dataSize=2 567646Sgene.wu@arm.com br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,) 577646Sgene.wu@arm.com ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8 587646Sgene.wu@arm.com br rom_local_label("%(startLabel)s_processDescriptor") 597646Sgene.wu@arm.com%(startLabel)s_globalDescriptor: 607646Sgene.wu@arm.com ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8 617646Sgene.wu@arm.com%(startLabel)s_processDescriptor: 627646Sgene.wu@arm.com chks t10, t3, IntCSCheck, dataSize=8 637646Sgene.wu@arm.com wrdl hs, t3, t10, dataSize=8 647646Sgene.wu@arm.com 657646Sgene.wu@arm.com # Stick the target offset in t9. 667646Sgene.wu@arm.com wrdh t9, t4, t2, dataSize=8 677646Sgene.wu@arm.com 687646Sgene.wu@arm.com 697646Sgene.wu@arm.com # 707646Sgene.wu@arm.com # Figure out where the stack should be 717646Sgene.wu@arm.com # 727646Sgene.wu@arm.com 737205Sgblack@eecs.umich.edu # Record what we might set the stack selector to. 747205Sgblack@eecs.umich.edu rdsel t11, ss 757205Sgblack@eecs.umich.edu 767205Sgblack@eecs.umich.edu # Check if we're changing privelege level. At this point we can assume 777205Sgblack@eecs.umich.edu # we're going to a DPL that's less than or equal to the CPL. 787205Sgblack@eecs.umich.edu rdattr t10, hs, dataSize=8 797205Sgblack@eecs.umich.edu srli t10, t10, 3, dataSize=8 807205Sgblack@eecs.umich.edu andi t10, t10, 3, dataSize=8 817205Sgblack@eecs.umich.edu rdattr t5, cs, dataSize=8 827205Sgblack@eecs.umich.edu srli t5, t5, 3, dataSize=8 837205Sgblack@eecs.umich.edu sub t5, t5, t10, dataSize=8 847205Sgblack@eecs.umich.edu andi t0, t5, 0x3, flags=(EZF,), dataSize=8 857205Sgblack@eecs.umich.edu # We're going to change priviledge, so zero out the stack selector. We 867205Sgblack@eecs.umich.edu # need to let the IST have priority so we don't branch yet. 877205Sgblack@eecs.umich.edu wrsel t11, t0, flags=(nCEZF,) 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.edu # Check the IST field of the gate descriptor 908442Sgblack@eecs.umich.edu srli t10, t4, 32, dataSize=8 918442Sgblack@eecs.umich.edu andi t10, t10, 0x7, dataSize=8 927205Sgblack@eecs.umich.edu subi t0, t10, 1, flags=(ECF,), dataSize=8 937205Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,) 947205Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,) 957205Sgblack@eecs.umich.edu 967205Sgblack@eecs.umich.edu # If we're here, it's because the stack isn't being switched. 977205Sgblack@eecs.umich.edu # Set t6 to the new aligned rsp. 987205Sgblack@eecs.umich.edu mov t6, rsp, dataSize=8 997205Sgblack@eecs.umich.edu andi t6, t6, 0xF0, dataSize=1 1007205Sgblack@eecs.umich.edu subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8 1017597Sminkyu.jeong@arm.com 1027597Sminkyu.jeong@arm.com # Check that we can access everything we need to on the stack 1037205Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8 1047205Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], \ 1057205Sgblack@eecs.umich.edu 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 1067205Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1077205Sgblack@eecs.umich.edu 1087205Sgblack@eecs.umich.edu%(startLabel)s_istStackSwitch: 1097205Sgblack@eecs.umich.edu panic "IST based stack switching isn't implemented" 1107205Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1117205Sgblack@eecs.umich.edu 1127205Sgblack@eecs.umich.edu%(startLabel)s_cplStackSwitch: 1137205Sgblack@eecs.umich.edu panic "CPL change initiated stack switching isn't implemented" 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edu%(startLabel)s_stackSwitched: 1167205Sgblack@eecs.umich.edu 1177205Sgblack@eecs.umich.edu 1187205Sgblack@eecs.umich.edu ## 1197205Sgblack@eecs.umich.edu ## Point of no return. 1207205Sgblack@eecs.umich.edu ## We're now going to irrevocably modify visible state. 1217205Sgblack@eecs.umich.edu ## Anything bad that's going to happen should have happened by now or will 1227205Sgblack@eecs.umich.edu ## happen right now. 1237205Sgblack@eecs.umich.edu ## 1247205Sgblack@eecs.umich.edu wrip t0, t9, dataSize=8 1257205Sgblack@eecs.umich.edu 1268442Sgblack@eecs.umich.edu 1278442Sgblack@eecs.umich.edu # 1287205Sgblack@eecs.umich.edu # Build up the interrupt stack frame 1297597Sminkyu.jeong@arm.com # 1307597Sminkyu.jeong@arm.com 1317205Sgblack@eecs.umich.edu 1327205Sgblack@eecs.umich.edu # Write out the contents of memory 1337205Sgblack@eecs.umich.edu %(errorCodeCode)s 1347205Sgblack@eecs.umich.edu st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 1357205Sgblack@eecs.umich.edu limm t5, 0, dataSize=8 1367205Sgblack@eecs.umich.edu rdsel t5, cs, dataSize=2 1377205Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8 1387205Sgblack@eecs.umich.edu rflags t10, dataSize=8 1397205Sgblack@eecs.umich.edu st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8 1407205Sgblack@eecs.umich.edu st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8 1417205Sgblack@eecs.umich.edu rdsel t5, ss, dataSize=2 1427205Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 1437205Sgblack@eecs.umich.edu 1447205Sgblack@eecs.umich.edu # Set the stack segment 1457205Sgblack@eecs.umich.edu mov rsp, rsp, t6, dataSize=8 1467205Sgblack@eecs.umich.edu wrsel ss, t11, dataSize=2 1477205Sgblack@eecs.umich.edu 1487205Sgblack@eecs.umich.edu # 1497205Sgblack@eecs.umich.edu # Set up the target code segment 1508442Sgblack@eecs.umich.edu # 1518442Sgblack@eecs.umich.edu srli t5, t4, 16, dataSize=8 1527205Sgblack@eecs.umich.edu andi t5, t5, 0xFF, dataSize=8 1537205Sgblack@eecs.umich.edu wrdl cs, t3, t5, dataSize=8 1547205Sgblack@eecs.umich.edu wrsel cs, t5, dataSize=2 1557205Sgblack@eecs.umich.edu 1567205Sgblack@eecs.umich.edu # 1577205Sgblack@eecs.umich.edu # Adjust rflags which is still in t10 from above 1587205Sgblack@eecs.umich.edu # 1597205Sgblack@eecs.umich.edu 1607205Sgblack@eecs.umich.edu # Set IF to the lowest bit of the original gate type. 1617205Sgblack@eecs.umich.edu # The type field of the original gate starts at bit 40. 1627205Sgblack@eecs.umich.edu 1637205Sgblack@eecs.umich.edu # Set the TF, NT, and RF bits. We'll flip them at the end. 1647119Sgblack@eecs.umich.edu limm t6, (1 << 8) | (1 << 14) | (1 << 16) 1657119Sgblack@eecs.umich.edu or t10, t10, t6 1667119Sgblack@eecs.umich.edu srli t5, t4, 40, dataSize=8 1677119Sgblack@eecs.umich.edu srli t7, t10, 9, dataSize=8 1687119Sgblack@eecs.umich.edu xor t5, t7, t5, dataSize=8 1697119Sgblack@eecs.umich.edu andi t5, t5, 1, dataSize=8 1707119Sgblack@eecs.umich.edu slli t5, t5, 9, dataSize=8 1717119Sgblack@eecs.umich.edu or t6, t5, t6, dataSize=8 1727119Sgblack@eecs.umich.edu 1737119Sgblack@eecs.umich.edu # Put the results into rflags 1747119Sgblack@eecs.umich.edu wrflags t6, t10 1757119Sgblack@eecs.umich.edu 1767119Sgblack@eecs.umich.edu eret 1777119Sgblack@eecs.umich.edu}; 1788442Sgblack@eecs.umich.edu''' 1797119Sgblack@eecs.umich.edu 1807119Sgblack@eecs.umich.edumicrocode = \ 1817119Sgblack@eecs.umich.eduintCodeTemplate % {\ 1827119Sgblack@eecs.umich.edu "startLabel" : "longModeInterrupt", 1837119Sgblack@eecs.umich.edu "gateCheckType" : "IntGateCheck", 1847119Sgblack@eecs.umich.edu "errorCodeSize" : 0, 1857597Sminkyu.jeong@arm.com "errorCodeCode" : "" 1867597Sminkyu.jeong@arm.com} + \ 1877119Sgblack@eecs.umich.eduintCodeTemplate % {\ 1887119Sgblack@eecs.umich.edu "startLabel" : "longModeSoftInterrupt", 1897119Sgblack@eecs.umich.edu "gateCheckType" : "SoftIntGateCheck", 1907119Sgblack@eecs.umich.edu "errorCodeSize" : 0, 1917119Sgblack@eecs.umich.edu "errorCodeCode" : "" 1927119Sgblack@eecs.umich.edu} + \ 1937639Sgblack@eecs.umich.eduintCodeTemplate % {\ 1947639Sgblack@eecs.umich.edu "startLabel" : "longModeInterruptWithError", 1957639Sgblack@eecs.umich.edu "gateCheckType" : "IntGateCheck", 1967639Sgblack@eecs.umich.edu "errorCodeSize" : 8, 1977639Sgblack@eecs.umich.edu "errorCodeCode" : ''' 1987639Sgblack@eecs.umich.edu st t15, hs, [1, t0, t6], dataSize=8, addressSize=8 1997639Sgblack@eecs.umich.edu ''' 2007639Sgblack@eecs.umich.edu} + \ 2017639Sgblack@eecs.umich.edu''' 2027639Sgblack@eecs.umich.edudef rom 2037639Sgblack@eecs.umich.edu{ 2047639Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in legacy mode. 2057639Sgblack@eecs.umich.edu extern legacyModeInterrupt: 2067639Sgblack@eecs.umich.edu panic "Legacy mode interrupts not implemented (in microcode)" 2077639Sgblack@eecs.umich.edu eret 2087639Sgblack@eecs.umich.edu}; 2097639Sgblack@eecs.umich.edu''' 2107639Sgblack@eecs.umich.edu