romutil.py revision 5680
15680Sgblack@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 25680Sgblack@eecs.umich.edu# All rights reserved. 35680Sgblack@eecs.umich.edu# 45680Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 55680Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 65680Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 75680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 85680Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 95680Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 105680Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 115680Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 125680Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 135680Sgblack@eecs.umich.edu# this software without specific prior written permission. 145680Sgblack@eecs.umich.edu# 155680Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165680Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175680Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185680Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195680Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205680Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215680Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225680Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235680Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245680Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255680Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265680Sgblack@eecs.umich.edu# 275680Sgblack@eecs.umich.edu# Authors: Gabe Black 285680Sgblack@eecs.umich.edu 295680Sgblack@eecs.umich.edumicrocode = ''' 305680Sgblack@eecs.umich.edudef rom 315680Sgblack@eecs.umich.edu{ 325680Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in long mode. 335680Sgblack@eecs.umich.edu # On entry, t1 is set to the vector of the interrupt and t7 is the current 345680Sgblack@eecs.umich.edu # ip. We need that because rdip returns the next ip. 355680Sgblack@eecs.umich.edu extern longModeInterrupt: 365680Sgblack@eecs.umich.edu 375680Sgblack@eecs.umich.edu # 385680Sgblack@eecs.umich.edu # Get the 64 bit interrupt or trap gate descriptor from the IDT 395680Sgblack@eecs.umich.edu # 405680Sgblack@eecs.umich.edu 415680Sgblack@eecs.umich.edu # Load the gate descriptor from the IDT 425680Sgblack@eecs.umich.edu slli t4, t1, 4, dataSize=8 435680Sgblack@eecs.umich.edu ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8 445680Sgblack@eecs.umich.edu ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8 455680Sgblack@eecs.umich.edu 465680Sgblack@eecs.umich.edu # Check permissions 475680Sgblack@eecs.umich.edu chks t1, t4, IntGateCheck 485680Sgblack@eecs.umich.edu 495680Sgblack@eecs.umich.edu mov t1, t1, t4, dataSize=8 505680Sgblack@eecs.umich.edu 515680Sgblack@eecs.umich.edu # Check that it's the right type 525680Sgblack@eecs.umich.edu srli t4, t1, 40, dataSize=8 535680Sgblack@eecs.umich.edu andi t4, t4, 0xe, dataSize=8 545680Sgblack@eecs.umich.edu xori t4, t4, 0xe, flags=(EZF,), dataSize=8 555680Sgblack@eecs.umich.edu fault "new GeneralProtection(0)", flags=(nCEZF,) 565680Sgblack@eecs.umich.edu 575680Sgblack@eecs.umich.edu 585680Sgblack@eecs.umich.edu # 595680Sgblack@eecs.umich.edu # Get the target CS descriptor using the selector in the gate 605680Sgblack@eecs.umich.edu # descriptor. 615680Sgblack@eecs.umich.edu # 625680Sgblack@eecs.umich.edu srli t4, t1, 16, dataSize=8 635680Sgblack@eecs.umich.edu andi t5, t4, 0xF8, dataSize=8 645680Sgblack@eecs.umich.edu andi t0, t4, 0x4, flags=(EZF,), dataSize=2 655680Sgblack@eecs.umich.edu br rom_local_label("globalDescriptor"), flags=(CEZF,) 665680Sgblack@eecs.umich.edu ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8 675680Sgblack@eecs.umich.edu br rom_local_label("processDescriptor") 685680Sgblack@eecs.umich.eduglobalDescriptor: 695680Sgblack@eecs.umich.edu ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8 705680Sgblack@eecs.umich.eduprocessDescriptor: 715680Sgblack@eecs.umich.edu chks t4, t3, IntCSCheck, dataSize=8 725680Sgblack@eecs.umich.edu wrdl hs, t3, t4, dataSize=8 735680Sgblack@eecs.umich.edu 745680Sgblack@eecs.umich.edu # Check that the target offset is in canonical form 755680Sgblack@eecs.umich.edu wrdh t4, t1, t2, dataSize=8 765680Sgblack@eecs.umich.edu srli t4, t4, 47, dataSize=8 775680Sgblack@eecs.umich.edu addi t4, t4, 1, dataSize=8 785680Sgblack@eecs.umich.edu srli t4, t4, 1, dataSize=8 795680Sgblack@eecs.umich.edu or t4, t4, t4, flags=(EZF,), dataSize=2 805680Sgblack@eecs.umich.edu fault "new GeneralProtection(0)", flags=(nCEZF,) 815680Sgblack@eecs.umich.edu 825680Sgblack@eecs.umich.edu 835680Sgblack@eecs.umich.edu # 845680Sgblack@eecs.umich.edu # Figure out where the stack should be 855680Sgblack@eecs.umich.edu # 865680Sgblack@eecs.umich.edu 875680Sgblack@eecs.umich.edu # Record what we might set the stack selector to. 885680Sgblack@eecs.umich.edu rdsel t6, ss 895680Sgblack@eecs.umich.edu wrsel hs, t6 905680Sgblack@eecs.umich.edu 915680Sgblack@eecs.umich.edu # Check if we're changing privelege level. At this point we can assume 925680Sgblack@eecs.umich.edu # we're going to a DPL that's less than or equal to the CPL. 935680Sgblack@eecs.umich.edu rdattr t4, hs, dataSize=8 945680Sgblack@eecs.umich.edu srli t4, t4, 3, dataSize=8 955680Sgblack@eecs.umich.edu andi t4, t4, 3, dataSize=8 965680Sgblack@eecs.umich.edu rdattr t5, cs, dataSize=8 975680Sgblack@eecs.umich.edu srli t5, t5, 3, dataSize=8 985680Sgblack@eecs.umich.edu sub t5, t5, t4, dataSize=8 995680Sgblack@eecs.umich.edu andi t0, t5, 0x3, flags=(EZF,), dataSize=8 1005680Sgblack@eecs.umich.edu # We're going to change priviledge, so zero out the stack selector. We 1015680Sgblack@eecs.umich.edu # need to let the IST have priority so we don't branch yet. 1025680Sgblack@eecs.umich.edu limm t4, 0 1035680Sgblack@eecs.umich.edu wrsel hs, t4, flags=(nCEZF,) 1045680Sgblack@eecs.umich.edu 1055680Sgblack@eecs.umich.edu # Check the IST field of the gate descriptor 1065680Sgblack@eecs.umich.edu srli t4, t1, 32, dataSize=8 1075680Sgblack@eecs.umich.edu andi t4, t4, 0x7, dataSize=8 1085680Sgblack@eecs.umich.edu subi t0, t4, 1, flags=(ECF,), dataSize=8 1095680Sgblack@eecs.umich.edu br rom_local_label("istStackSwitch"), flags=(nCECF,) 1105680Sgblack@eecs.umich.edu br rom_local_label("cplStackSwitch"), flags=(nCEZF,) 1115680Sgblack@eecs.umich.edu 1125680Sgblack@eecs.umich.edu # If we're here, it's because the stack isn't being switched. 1135680Sgblack@eecs.umich.edu # Set t6 to the new rsp. 1145680Sgblack@eecs.umich.edu subi t6, rsp, 40, dataSize=8 1155680Sgblack@eecs.umich.edu 1165680Sgblack@eecs.umich.edu # Align the stack 1175680Sgblack@eecs.umich.edu andi t6, t6, 0xF0, dataSize=1 1185680Sgblack@eecs.umich.edu 1195680Sgblack@eecs.umich.edu # Check that we can access everything we need to on the stack 1205680Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8 1215680Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], 32, dataSize=8, addressSize=8 1225680Sgblack@eecs.umich.edu br rom_local_label("stackSwitched") 1235680Sgblack@eecs.umich.edu 1245680Sgblack@eecs.umich.eduistStackSwitch: 1255680Sgblack@eecs.umich.edu panic "IST based stack switching isn't implemented" 1265680Sgblack@eecs.umich.edu br rom_local_label("stackSwitched") 1275680Sgblack@eecs.umich.edu 1285680Sgblack@eecs.umich.educplStackSwitch: 1295680Sgblack@eecs.umich.edu panic "CPL change initiated stack switching isn't implemented" 1305680Sgblack@eecs.umich.edu 1315680Sgblack@eecs.umich.edustackSwitched: 1325680Sgblack@eecs.umich.edu 1335680Sgblack@eecs.umich.edu 1345680Sgblack@eecs.umich.edu ## 1355680Sgblack@eecs.umich.edu ## Point of no return. 1365680Sgblack@eecs.umich.edu ## We're now going to irrevocably modify visible state. 1375680Sgblack@eecs.umich.edu ## Anything bad that's going to happen should have happened by now. 1385680Sgblack@eecs.umich.edu ## 1395680Sgblack@eecs.umich.edu 1405680Sgblack@eecs.umich.edu 1415680Sgblack@eecs.umich.edu # 1425680Sgblack@eecs.umich.edu # Build up the interrupt stack frame 1435680Sgblack@eecs.umich.edu # 1445680Sgblack@eecs.umich.edu 1455680Sgblack@eecs.umich.edu # Write out the contents of memory 1465680Sgblack@eecs.umich.edu st t7, hs, [1, t0, t6], dataSize=8 1475680Sgblack@eecs.umich.edu limm t5, 0, dataSize=8 1485680Sgblack@eecs.umich.edu rdsel t5, cs, dataSize=2 1495680Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 8, dataSize=8 1505680Sgblack@eecs.umich.edu rflags t4, dataSize=8 1515680Sgblack@eecs.umich.edu st t4, hs, [1, t0, t6], 16, dataSize=8 1525680Sgblack@eecs.umich.edu st rsp, hs, [1, t0, t6], 24, dataSize=8 1535680Sgblack@eecs.umich.edu rdsel t5, ss, dataSize=2 1545680Sgblack@eecs.umich.edu st t5, hs, [1, t0, t6], 32, dataSize=8 1555680Sgblack@eecs.umich.edu 1565680Sgblack@eecs.umich.edu # Set the stack segment 1575680Sgblack@eecs.umich.edu mov rsp, rsp, t6, dataSize=8 1585680Sgblack@eecs.umich.edu rdsel t7, hs, dataSize=2 1595680Sgblack@eecs.umich.edu wrsel ss, t7, dataSize=2 1605680Sgblack@eecs.umich.edu 1615680Sgblack@eecs.umich.edu # 1625680Sgblack@eecs.umich.edu # Set up the target code segment 1635680Sgblack@eecs.umich.edu # 1645680Sgblack@eecs.umich.edu srli t5, t1, 16, dataSize=8 1655680Sgblack@eecs.umich.edu andi t5, t5, 0xFF, dataSize=8 1665680Sgblack@eecs.umich.edu wrdl cs, t3, t5, dataSize=8 1675680Sgblack@eecs.umich.edu wrsel cs, t5, dataSize=2 1685680Sgblack@eecs.umich.edu wrdh t7, t1, t2, dataSize=8 1695680Sgblack@eecs.umich.edu wrip t0, t7, dataSize=8 1705680Sgblack@eecs.umich.edu 1715680Sgblack@eecs.umich.edu # 1725680Sgblack@eecs.umich.edu # Adjust rflags which is still in t4 from above 1735680Sgblack@eecs.umich.edu # 1745680Sgblack@eecs.umich.edu 1755680Sgblack@eecs.umich.edu # Set IF to the lowest bit of the original gate type. 1765680Sgblack@eecs.umich.edu # The type field of the original gate starts at bit 40. 1775680Sgblack@eecs.umich.edu 1785680Sgblack@eecs.umich.edu # Set the TF, NT, and RF bits. We'll flip them at the end. 1795680Sgblack@eecs.umich.edu limm t6, (1 << 8) | (1 << 14) | (1 << 16) 1805680Sgblack@eecs.umich.edu or t4, t4, t6 1815680Sgblack@eecs.umich.edu srli t5, t1, 40, dataSize=8 1825680Sgblack@eecs.umich.edu srli t7, t4, 9, dataSize=8 1835680Sgblack@eecs.umich.edu xor t5, t7, t5, dataSize=8 1845680Sgblack@eecs.umich.edu andi t5, t5, 1, dataSize=8 1855680Sgblack@eecs.umich.edu slli t5, t5, 9, dataSize=8 1865680Sgblack@eecs.umich.edu or t6, t5, t6, dataSize=8 1875680Sgblack@eecs.umich.edu 1885680Sgblack@eecs.umich.edu # Put the results into rflags 1895680Sgblack@eecs.umich.edu wrflags t6, t4 1905680Sgblack@eecs.umich.edu 1915680Sgblack@eecs.umich.edu eret 1925680Sgblack@eecs.umich.edu}; 1935680Sgblack@eecs.umich.edu 1945680Sgblack@eecs.umich.edudef rom 1955680Sgblack@eecs.umich.edu{ 1965680Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in legacy mode. 1975680Sgblack@eecs.umich.edu extern legacyModeInterrupt: 1985680Sgblack@eecs.umich.edu panic "Legacy mode interrupts not implemented (in microcode)" 1995680Sgblack@eecs.umich.edu eret 2005680Sgblack@eecs.umich.edu}; 2015680Sgblack@eecs.umich.edu''' 202