semaphores.py revision 6094:28198ab3adec 
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
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39# notice to acknowledge the contribution from this software where
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41#
42# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53#
54# Authors: Gabe Black
55
56microcode = '''
57def macroop CMPXCHG_R_R {
58    sub t0, rax, reg, flags=(OF, SF, ZF, AF, PF, CF)
59    mov reg, reg, regm, flags=(CZF,)
60    mov rax, rax, reg, flags=(nCZF,)
61};
62
63def macroop CMPXCHG_M_R {
64    ldst t1, seg, sib, disp
65    sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
66
67    mov t1, t1, reg, flags=(CZF,)
68    st t1, seg, sib, disp
69    mov rax, rax, t1, flags=(nCZF,)
70};
71
72def macroop CMPXCHG_P_R {
73    rdip t7
74    ldst t1, seg, riprel, disp
75    sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
76
77    mov t1, t1, reg, flags=(CZF,)
78    st t1, seg, riprel, disp
79    mov rax, rax, t1, flags=(nCZF,)
80};
81
82def macroop CMPXCHG_LOCKED_M_R {
83    ldstl t1, seg, sib, disp
84    sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
85
86    mov t1, t1, reg, flags=(CZF,)
87    stul t1, seg, sib, disp
88    mov rax, rax, t1, flags=(nCZF,)
89};
90
91def macroop CMPXCHG_LOCKED_P_R {
92    rdip t7
93    ldstl t1, seg, riprel, disp
94    sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
95
96    mov t1, t1, reg, flags=(CZF,)
97    stul t1, seg, riprel, disp
98    mov rax, rax, t1, flags=(nCZF,)
99};
100
101def macroop XADD_M_R {
102    ldst t1, seg, sib, disp
103    add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
104    st t2, seg, sib, disp
105    mov reg, reg, t1
106};
107
108def macroop XADD_P_R {
109    rdip t7
110    ldst t1, seg, riprel, disp
111    add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
112    st t2, seg, riprel, disp
113    mov reg, reg, t1
114};
115
116def macroop XADD_R_R {
117    add t2, regm, reg, flags=(OF,SF,ZF,AF,PF,CF)
118    mov regm, regm, reg
119    mov reg, reg, t2
120};
121
122'''
123#let {{
124#    class XCHG(Inst):
125#       "GenFault ${new UnimpInstFault}"
126#}};
127