monitor_mwait.isa revision 10529:05b5a6cf3521
1// Copyright (c) AMD 2// All rights reserved. 3// 4// Authors: Marc Orr 5 6// Monitor Instruction 7 8output header {{ 9 class MonitorInst : public X86ISA::X86StaticInst 10 { 11 public: 12 static const RegIndex foldOBit = 0; 13 /// Constructor 14 MonitorInst(const char *_mnemonic, ExtMachInst _machInst, 15 OpClass __opClass) : 16 X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass) 17 { } 18 19 std::string generateDisassembly(Addr pc, 20 const SymbolTable *symtab) const; 21 }; 22}}; 23 24output decoder {{ 25 std::string MonitorInst::generateDisassembly(Addr PC, 26 const SymbolTable *symtab) const 27 { 28 std::stringstream response; 29 30 printMnemonic(response, mnemonic); 31 ccprintf(response, " "); 32 printReg(response, _srcRegIdx[0], machInst.opSize); 33 return response.str(); 34 } 35}}; 36 37def format MonitorInst(code, *opt_flags) {{ 38 iop = InstObjParams(name, Name, 'MonitorInst', code, opt_flags) 39 header_output = BasicDeclare.subst(iop) 40 decoder_output = BasicConstructor.subst(iop) 41 decode_block = BasicDecode.subst(iop) 42 exec_output = BasicExecute.subst(iop) 43}}; 44 45 46// Mwait instruction 47 48// Declarations for execute() methods. 49def template MwaitExecDeclare {{ 50 Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; 51 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 52 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, 53 Trace::InstRecord *) const; 54}}; 55 56def template MwaitDeclare {{ 57 class %(class_name)s : public %(base_class)s 58 { 59 public: 60 // Constructor. 61 %(class_name)s(ExtMachInst machInst); 62 %(MwaitExecDeclare)s 63 }; 64}}; 65 66def template MwaitInitiateAcc {{ 67 Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, 68 Trace::InstRecord * traceData) const 69 { 70 uint64_t m = 0; //mem 71 unsigned s = 0x8; //size 72 unsigned f = 0; //flags 73 readMemTiming(xc, traceData, xc->getAddrMonitor()->vAddr, m, s, f); 74 return NoFault; 75 } 76}}; 77 78def template MwaitCompleteAcc {{ 79 Fault %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc, 80 Trace::InstRecord *traceData) const 81 { 82 MicroHalt hltObj(machInst, mnemonic, 0x0); 83 if(xc->mwait(pkt)) { 84 hltObj.execute(xc, traceData); 85 } 86 return NoFault; 87 } 88}}; 89 90output header {{ 91 class MwaitInst : public X86ISA::X86StaticInst 92 { 93 public: 94 static const RegIndex foldOBit = 0; 95 /// Constructor 96 MwaitInst(const char *_mnemonic, ExtMachInst _machInst, 97 OpClass __opClass) : 98 X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass) 99 { 100 flags[IsMemRef] = 1; 101 flags[IsLoad] = 1; 102 } 103 104 std::string generateDisassembly(Addr pc, 105 const SymbolTable *symtab) const; 106 }; 107}}; 108 109output decoder {{ 110 std::string MwaitInst::generateDisassembly(Addr PC, 111 const SymbolTable *symtab) const 112 { 113 std::stringstream response; 114 115 printMnemonic(response, mnemonic); 116 ccprintf(response, " "); 117 printReg(response, _srcRegIdx[0], machInst.opSize); 118 return response.str(); 119 } 120}}; 121 122def format MwaitInst(code, *opt_flags) {{ 123 iop = InstObjParams(name, Name, 'MwaitInst', code, opt_flags) 124 header_output = MwaitDeclare.subst(iop) 125 decoder_output = BasicConstructor.subst(iop) 126 decode_block = BasicDecode.subst(iop) 127 exec_output = BasicExecute.subst(iop) 128 exec_output += MwaitInitiateAcc.subst(iop) 129 exec_output += MwaitCompleteAcc.subst(iop) 130}}; 131 132