isa.hh revision 11168:f98eb2da15a4 
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_ISA_HH__
32#define __ARCH_X86_ISA_HH__
33
34#include <iostream>
35#include <string>
36
37#include "arch/x86/regs/float.hh"
38#include "arch/x86/regs/misc.hh"
39#include "arch/x86/registers.hh"
40#include "base/types.hh"
41#include "sim/sim_object.hh"
42
43class Checkpoint;
44class EventManager;
45class ThreadContext;
46struct X86ISAParams;
47
48namespace X86ISA
49{
50    class ISA : public SimObject
51    {
52      protected:
53        MiscReg regVal[NUM_MISCREGS];
54        void updateHandyM5Reg(Efer efer, CR0 cr0,
55                SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
56                ThreadContext *tc);
57
58      public:
59        typedef X86ISAParams Params;
60
61        void clear();
62
63        ISA(Params *p);
64        const Params *params() const;
65
66        MiscReg readMiscRegNoEffect(int miscReg) const;
67        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
68
69        void setMiscRegNoEffect(int miscReg, MiscReg val);
70        void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
71
72        int
73        flattenIntIndex(int reg) const
74        {
75            return reg & ~IntFoldBit;
76        }
77
78        int
79        flattenFloatIndex(int reg) const
80        {
81            if (reg >= NUM_FLOATREGS) {
82                reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
83                                     regVal[MISCREG_X87_TOP]);
84            }
85            return reg;
86        }
87
88        int
89        flattenCCIndex(int reg) const
90        {
91            return reg;
92        }
93
94        int
95        flattenMiscIndex(int reg) const
96        {
97            return reg;
98        }
99
100        void serialize(CheckpointOut &cp) const override;
101        void unserialize(CheckpointIn &cp) override;
102
103        void startup(ThreadContext *tc);
104
105        /// Explicitly import the otherwise hidden startup
106        using SimObject::startup;
107
108    };
109}
110
111#endif
112