isa.cc revision 9376
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 319376Sgblack@eecs.umich.edu#include "arch/x86/decoder.hh" 326313Sgblack@eecs.umich.edu#include "arch/x86/isa.hh" 336336Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 346336Sgblack@eecs.umich.edu#include "cpu/base.hh" 356313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 366336Sgblack@eecs.umich.edu#include "sim/serialize.hh" 376313Sgblack@eecs.umich.edu 386313Sgblack@eecs.umich.edunamespace X86ISA 396313Sgblack@eecs.umich.edu{ 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.eduvoid 426336Sgblack@eecs.umich.eduISA::updateHandyM5Reg(Efer efer, CR0 cr0, 439376Sgblack@eecs.umich.edu SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, 449376Sgblack@eecs.umich.edu ThreadContext *tc) 456336Sgblack@eecs.umich.edu{ 466712Snate@binkert.org HandyM5Reg m5reg = 0; 476336Sgblack@eecs.umich.edu if (efer.lma) { 486336Sgblack@eecs.umich.edu m5reg.mode = LongMode; 496336Sgblack@eecs.umich.edu if (csAttr.longMode) 506336Sgblack@eecs.umich.edu m5reg.submode = SixtyFourBitMode; 516336Sgblack@eecs.umich.edu else 526336Sgblack@eecs.umich.edu m5reg.submode = CompatabilityMode; 536336Sgblack@eecs.umich.edu } else { 546336Sgblack@eecs.umich.edu m5reg.mode = LegacyMode; 556336Sgblack@eecs.umich.edu if (cr0.pe) { 566336Sgblack@eecs.umich.edu if (rflags.vm) 576336Sgblack@eecs.umich.edu m5reg.submode = Virtual8086Mode; 586336Sgblack@eecs.umich.edu else 596336Sgblack@eecs.umich.edu m5reg.submode = ProtectedMode; 606336Sgblack@eecs.umich.edu } else { 616336Sgblack@eecs.umich.edu m5reg.submode = RealMode; 626336Sgblack@eecs.umich.edu } 636336Sgblack@eecs.umich.edu } 646336Sgblack@eecs.umich.edu m5reg.cpl = csAttr.dpl; 656336Sgblack@eecs.umich.edu m5reg.paging = cr0.pg; 666336Sgblack@eecs.umich.edu m5reg.prot = cr0.pe; 676336Sgblack@eecs.umich.edu 686336Sgblack@eecs.umich.edu // Compute the default and alternate operand size. 696336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 706336Sgblack@eecs.umich.edu m5reg.defOp = 2; 716336Sgblack@eecs.umich.edu m5reg.altOp = 1; 726336Sgblack@eecs.umich.edu } else { 736336Sgblack@eecs.umich.edu m5reg.defOp = 1; 746336Sgblack@eecs.umich.edu m5reg.altOp = 2; 756336Sgblack@eecs.umich.edu } 766336Sgblack@eecs.umich.edu 776336Sgblack@eecs.umich.edu // Compute the default and alternate address size. 786336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 796336Sgblack@eecs.umich.edu m5reg.defAddr = 3; 806336Sgblack@eecs.umich.edu m5reg.altAddr = 2; 816336Sgblack@eecs.umich.edu } else if (csAttr.defaultSize) { 826336Sgblack@eecs.umich.edu m5reg.defAddr = 2; 836336Sgblack@eecs.umich.edu m5reg.altAddr = 1; 846336Sgblack@eecs.umich.edu } else { 856336Sgblack@eecs.umich.edu m5reg.defAddr = 1; 866336Sgblack@eecs.umich.edu m5reg.altAddr = 2; 876336Sgblack@eecs.umich.edu } 886336Sgblack@eecs.umich.edu 896336Sgblack@eecs.umich.edu // Compute the stack size 906336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 916336Sgblack@eecs.umich.edu m5reg.stack = 3; 926336Sgblack@eecs.umich.edu } else if (ssAttr.defaultSize) { 936336Sgblack@eecs.umich.edu m5reg.stack = 2; 946336Sgblack@eecs.umich.edu } else { 956336Sgblack@eecs.umich.edu m5reg.stack = 1; 966336Sgblack@eecs.umich.edu } 976336Sgblack@eecs.umich.edu 986336Sgblack@eecs.umich.edu regVal[MISCREG_M5_REG] = m5reg; 999376Sgblack@eecs.umich.edu if (tc) 1009376Sgblack@eecs.umich.edu tc->getDecoderPtr()->setM5Reg(m5reg); 1016336Sgblack@eecs.umich.edu} 1026336Sgblack@eecs.umich.edu 1036336Sgblack@eecs.umich.eduvoid 1046313Sgblack@eecs.umich.eduISA::clear() 1056313Sgblack@eecs.umich.edu{ 1066336Sgblack@eecs.umich.edu // Blank everything. 0 might not be an appropriate value for some things, 1076336Sgblack@eecs.umich.edu // but it is for most. 1086336Sgblack@eecs.umich.edu memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 1096336Sgblack@eecs.umich.edu regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 1106336Sgblack@eecs.umich.edu regVal[MISCREG_DR7] = 1 << 10; 1116313Sgblack@eecs.umich.edu} 1126313Sgblack@eecs.umich.edu 1136313Sgblack@eecs.umich.eduMiscReg 1146313Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 1156313Sgblack@eecs.umich.edu{ 1166336Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 1176336Sgblack@eecs.umich.edu // Instructions should filter out these indexes, and nothing else should 1186336Sgblack@eecs.umich.edu // attempt to read them directly. 1196336Sgblack@eecs.umich.edu assert( miscReg != MISCREG_CR1 && 1206336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR4 && 1216336Sgblack@eecs.umich.edu miscReg < MISCREG_CR8) && 1226336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR8 && 1236336Sgblack@eecs.umich.edu miscReg <= MISCREG_CR15)); 1246336Sgblack@eecs.umich.edu 1256336Sgblack@eecs.umich.edu return regVal[miscReg]; 1266313Sgblack@eecs.umich.edu} 1276313Sgblack@eecs.umich.edu 1286313Sgblack@eecs.umich.eduMiscReg 1296336Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 1306313Sgblack@eecs.umich.edu{ 1316336Sgblack@eecs.umich.edu if (miscReg == MISCREG_TSC) { 1326336Sgblack@eecs.umich.edu return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 1336336Sgblack@eecs.umich.edu } 1349372Snilay@cs.wisc.edu 1359372Snilay@cs.wisc.edu if (miscReg == MISCREG_FSW) { 1369372Snilay@cs.wisc.edu MiscReg fsw = regVal[MISCREG_FSW]; 1379372Snilay@cs.wisc.edu MiscReg top = regVal[MISCREG_X87_TOP]; 1389372Snilay@cs.wisc.edu return (fsw & (~(7ULL << 11))) + (top << 11); 1399372Snilay@cs.wisc.edu } 1409372Snilay@cs.wisc.edu 1416336Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 1426313Sgblack@eecs.umich.edu} 1436313Sgblack@eecs.umich.edu 1446313Sgblack@eecs.umich.eduvoid 1456336Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 1466313Sgblack@eecs.umich.edu{ 1476336Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 1486336Sgblack@eecs.umich.edu // Instructions should filter out these indexes, and nothing else should 1496336Sgblack@eecs.umich.edu // attempt to write to them directly. 1506336Sgblack@eecs.umich.edu assert( miscReg != MISCREG_CR1 && 1516336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR4 && 1526336Sgblack@eecs.umich.edu miscReg < MISCREG_CR8) && 1536336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR8 && 1546336Sgblack@eecs.umich.edu miscReg <= MISCREG_CR15)); 1556336Sgblack@eecs.umich.edu regVal[miscReg] = val; 1566313Sgblack@eecs.umich.edu} 1576313Sgblack@eecs.umich.edu 1586313Sgblack@eecs.umich.eduvoid 1596336Sgblack@eecs.umich.eduISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 1606313Sgblack@eecs.umich.edu{ 1616336Sgblack@eecs.umich.edu MiscReg newVal = val; 1626336Sgblack@eecs.umich.edu switch(miscReg) 1636336Sgblack@eecs.umich.edu { 1646336Sgblack@eecs.umich.edu case MISCREG_CR0: 1656336Sgblack@eecs.umich.edu { 1666336Sgblack@eecs.umich.edu CR0 toggled = regVal[miscReg] ^ val; 1676336Sgblack@eecs.umich.edu CR0 newCR0 = val; 1686336Sgblack@eecs.umich.edu Efer efer = regVal[MISCREG_EFER]; 1696336Sgblack@eecs.umich.edu if (toggled.pg && efer.lme) { 1706336Sgblack@eecs.umich.edu if (newCR0.pg) { 1716336Sgblack@eecs.umich.edu //Turning on long mode 1726336Sgblack@eecs.umich.edu efer.lma = 1; 1736336Sgblack@eecs.umich.edu regVal[MISCREG_EFER] = efer; 1746336Sgblack@eecs.umich.edu } else { 1756336Sgblack@eecs.umich.edu //Turning off long mode 1766336Sgblack@eecs.umich.edu efer.lma = 0; 1776336Sgblack@eecs.umich.edu regVal[MISCREG_EFER] = efer; 1786336Sgblack@eecs.umich.edu } 1796336Sgblack@eecs.umich.edu } 1806336Sgblack@eecs.umich.edu if (toggled.pg) { 1816336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateAll(); 1826336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateAll(); 1836336Sgblack@eecs.umich.edu } 1846336Sgblack@eecs.umich.edu //This must always be 1. 1856336Sgblack@eecs.umich.edu newCR0.et = 1; 1866336Sgblack@eecs.umich.edu newVal = newCR0; 1876336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 1886336Sgblack@eecs.umich.edu newCR0, 1896336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 1906336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 1919376Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS], 1929376Sgblack@eecs.umich.edu tc); 1936336Sgblack@eecs.umich.edu } 1946336Sgblack@eecs.umich.edu break; 1956336Sgblack@eecs.umich.edu case MISCREG_CR2: 1966336Sgblack@eecs.umich.edu break; 1976336Sgblack@eecs.umich.edu case MISCREG_CR3: 1986336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateNonGlobal(); 1996336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateNonGlobal(); 2006336Sgblack@eecs.umich.edu break; 2016336Sgblack@eecs.umich.edu case MISCREG_CR4: 2026336Sgblack@eecs.umich.edu { 2036336Sgblack@eecs.umich.edu CR4 toggled = regVal[miscReg] ^ val; 2046336Sgblack@eecs.umich.edu if (toggled.pae || toggled.pse || toggled.pge) { 2056336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateAll(); 2066336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateAll(); 2076336Sgblack@eecs.umich.edu } 2086336Sgblack@eecs.umich.edu } 2096336Sgblack@eecs.umich.edu break; 2106336Sgblack@eecs.umich.edu case MISCREG_CR8: 2116336Sgblack@eecs.umich.edu break; 2126336Sgblack@eecs.umich.edu case MISCREG_CS_ATTR: 2136336Sgblack@eecs.umich.edu { 2146336Sgblack@eecs.umich.edu SegAttr toggled = regVal[miscReg] ^ val; 2156336Sgblack@eecs.umich.edu SegAttr newCSAttr = val; 2166336Sgblack@eecs.umich.edu if (toggled.longMode) { 2176336Sgblack@eecs.umich.edu if (newCSAttr.longMode) { 2186336Sgblack@eecs.umich.edu regVal[MISCREG_ES_EFF_BASE] = 0; 2196336Sgblack@eecs.umich.edu regVal[MISCREG_CS_EFF_BASE] = 0; 2206336Sgblack@eecs.umich.edu regVal[MISCREG_SS_EFF_BASE] = 0; 2216336Sgblack@eecs.umich.edu regVal[MISCREG_DS_EFF_BASE] = 0; 2226336Sgblack@eecs.umich.edu } else { 2236336Sgblack@eecs.umich.edu regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 2246336Sgblack@eecs.umich.edu regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 2256336Sgblack@eecs.umich.edu regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 2266336Sgblack@eecs.umich.edu regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 2276336Sgblack@eecs.umich.edu } 2286336Sgblack@eecs.umich.edu } 2296336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 2306336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 2316336Sgblack@eecs.umich.edu newCSAttr, 2326336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 2339376Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS], 2349376Sgblack@eecs.umich.edu tc); 2356336Sgblack@eecs.umich.edu } 2366336Sgblack@eecs.umich.edu break; 2376336Sgblack@eecs.umich.edu case MISCREG_SS_ATTR: 2386336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 2396336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 2406336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 2416336Sgblack@eecs.umich.edu val, 2429376Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS], 2439376Sgblack@eecs.umich.edu tc); 2446336Sgblack@eecs.umich.edu break; 2456336Sgblack@eecs.umich.edu // These segments always actually use their bases, or in other words 2466336Sgblack@eecs.umich.edu // their effective bases must stay equal to their actual bases. 2476336Sgblack@eecs.umich.edu case MISCREG_FS_BASE: 2486336Sgblack@eecs.umich.edu case MISCREG_GS_BASE: 2496336Sgblack@eecs.umich.edu case MISCREG_HS_BASE: 2506336Sgblack@eecs.umich.edu case MISCREG_TSL_BASE: 2516336Sgblack@eecs.umich.edu case MISCREG_TSG_BASE: 2526336Sgblack@eecs.umich.edu case MISCREG_TR_BASE: 2536336Sgblack@eecs.umich.edu case MISCREG_IDTR_BASE: 2546336Sgblack@eecs.umich.edu regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 2556336Sgblack@eecs.umich.edu break; 2566336Sgblack@eecs.umich.edu // These segments ignore their bases in 64 bit mode. 2576336Sgblack@eecs.umich.edu // their effective bases must stay equal to their actual bases. 2586336Sgblack@eecs.umich.edu case MISCREG_ES_BASE: 2596336Sgblack@eecs.umich.edu case MISCREG_CS_BASE: 2606336Sgblack@eecs.umich.edu case MISCREG_SS_BASE: 2616336Sgblack@eecs.umich.edu case MISCREG_DS_BASE: 2626336Sgblack@eecs.umich.edu { 2636336Sgblack@eecs.umich.edu Efer efer = regVal[MISCREG_EFER]; 2646336Sgblack@eecs.umich.edu SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 2656336Sgblack@eecs.umich.edu if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 2666336Sgblack@eecs.umich.edu regVal[MISCREG_SEG_EFF_BASE(miscReg - 2676336Sgblack@eecs.umich.edu MISCREG_SEG_BASE_BASE)] = val; 2686336Sgblack@eecs.umich.edu } 2696336Sgblack@eecs.umich.edu break; 2706336Sgblack@eecs.umich.edu case MISCREG_TSC: 2716336Sgblack@eecs.umich.edu regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 2726336Sgblack@eecs.umich.edu return; 2736336Sgblack@eecs.umich.edu case MISCREG_DR0: 2746336Sgblack@eecs.umich.edu case MISCREG_DR1: 2756336Sgblack@eecs.umich.edu case MISCREG_DR2: 2766336Sgblack@eecs.umich.edu case MISCREG_DR3: 2776336Sgblack@eecs.umich.edu /* These should eventually set up breakpoints. */ 2786336Sgblack@eecs.umich.edu break; 2796336Sgblack@eecs.umich.edu case MISCREG_DR4: 2806336Sgblack@eecs.umich.edu miscReg = MISCREG_DR6; 2816336Sgblack@eecs.umich.edu /* Fall through to have the same effects as DR6. */ 2826336Sgblack@eecs.umich.edu case MISCREG_DR6: 2836336Sgblack@eecs.umich.edu { 2846336Sgblack@eecs.umich.edu DR6 dr6 = regVal[MISCREG_DR6]; 2856336Sgblack@eecs.umich.edu DR6 newDR6 = val; 2866336Sgblack@eecs.umich.edu dr6.b0 = newDR6.b0; 2876336Sgblack@eecs.umich.edu dr6.b1 = newDR6.b1; 2886336Sgblack@eecs.umich.edu dr6.b2 = newDR6.b2; 2896336Sgblack@eecs.umich.edu dr6.b3 = newDR6.b3; 2906336Sgblack@eecs.umich.edu dr6.bd = newDR6.bd; 2916336Sgblack@eecs.umich.edu dr6.bs = newDR6.bs; 2926336Sgblack@eecs.umich.edu dr6.bt = newDR6.bt; 2936336Sgblack@eecs.umich.edu newVal = dr6; 2946336Sgblack@eecs.umich.edu } 2956336Sgblack@eecs.umich.edu break; 2966336Sgblack@eecs.umich.edu case MISCREG_DR5: 2976336Sgblack@eecs.umich.edu miscReg = MISCREG_DR7; 2986336Sgblack@eecs.umich.edu /* Fall through to have the same effects as DR7. */ 2996336Sgblack@eecs.umich.edu case MISCREG_DR7: 3006336Sgblack@eecs.umich.edu { 3016336Sgblack@eecs.umich.edu DR7 dr7 = regVal[MISCREG_DR7]; 3026336Sgblack@eecs.umich.edu DR7 newDR7 = val; 3036336Sgblack@eecs.umich.edu dr7.l0 = newDR7.l0; 3046336Sgblack@eecs.umich.edu dr7.g0 = newDR7.g0; 3056336Sgblack@eecs.umich.edu if (dr7.l0 || dr7.g0) { 3066336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3076336Sgblack@eecs.umich.edu } else { 3086336Sgblack@eecs.umich.edu /* Disable breakpoint 0. */ 3096336Sgblack@eecs.umich.edu } 3106336Sgblack@eecs.umich.edu dr7.l1 = newDR7.l1; 3116336Sgblack@eecs.umich.edu dr7.g1 = newDR7.g1; 3126336Sgblack@eecs.umich.edu if (dr7.l1 || dr7.g1) { 3136336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3146336Sgblack@eecs.umich.edu } else { 3156336Sgblack@eecs.umich.edu /* Disable breakpoint 1. */ 3166336Sgblack@eecs.umich.edu } 3176336Sgblack@eecs.umich.edu dr7.l2 = newDR7.l2; 3186336Sgblack@eecs.umich.edu dr7.g2 = newDR7.g2; 3196336Sgblack@eecs.umich.edu if (dr7.l2 || dr7.g2) { 3206336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3216336Sgblack@eecs.umich.edu } else { 3226336Sgblack@eecs.umich.edu /* Disable breakpoint 2. */ 3236336Sgblack@eecs.umich.edu } 3246336Sgblack@eecs.umich.edu dr7.l3 = newDR7.l3; 3256336Sgblack@eecs.umich.edu dr7.g3 = newDR7.g3; 3266336Sgblack@eecs.umich.edu if (dr7.l3 || dr7.g3) { 3276336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3286336Sgblack@eecs.umich.edu } else { 3296336Sgblack@eecs.umich.edu /* Disable breakpoint 3. */ 3306336Sgblack@eecs.umich.edu } 3316336Sgblack@eecs.umich.edu dr7.gd = newDR7.gd; 3326336Sgblack@eecs.umich.edu dr7.rw0 = newDR7.rw0; 3336336Sgblack@eecs.umich.edu dr7.len0 = newDR7.len0; 3346336Sgblack@eecs.umich.edu dr7.rw1 = newDR7.rw1; 3356336Sgblack@eecs.umich.edu dr7.len1 = newDR7.len1; 3366336Sgblack@eecs.umich.edu dr7.rw2 = newDR7.rw2; 3376336Sgblack@eecs.umich.edu dr7.len2 = newDR7.len2; 3386336Sgblack@eecs.umich.edu dr7.rw3 = newDR7.rw3; 3396336Sgblack@eecs.umich.edu dr7.len3 = newDR7.len3; 3406336Sgblack@eecs.umich.edu } 3416336Sgblack@eecs.umich.edu break; 3426336Sgblack@eecs.umich.edu case MISCREG_M5_REG: 3436336Sgblack@eecs.umich.edu // Writing anything to the m5reg with side effects makes it update 3446336Sgblack@eecs.umich.edu // based on the current values of the relevant registers. The actual 3456336Sgblack@eecs.umich.edu // value written is discarded. 3466336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 3476336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 3486336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 3496336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 3509376Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS], 3519376Sgblack@eecs.umich.edu tc); 3526336Sgblack@eecs.umich.edu return; 3536336Sgblack@eecs.umich.edu default: 3546336Sgblack@eecs.umich.edu break; 3556336Sgblack@eecs.umich.edu } 3566336Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, newVal); 3576336Sgblack@eecs.umich.edu} 3586336Sgblack@eecs.umich.edu 3596336Sgblack@eecs.umich.eduvoid 3606336Sgblack@eecs.umich.eduISA::serialize(EventManager *em, std::ostream & os) 3616336Sgblack@eecs.umich.edu{ 3626336Sgblack@eecs.umich.edu SERIALIZE_ARRAY(regVal, NumMiscRegs); 3636336Sgblack@eecs.umich.edu} 3646336Sgblack@eecs.umich.edu 3656336Sgblack@eecs.umich.eduvoid 3666336Sgblack@eecs.umich.eduISA::unserialize(EventManager *em, Checkpoint * cp, 3676336Sgblack@eecs.umich.edu const std::string & section) 3686336Sgblack@eecs.umich.edu{ 3696336Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 3707533Ssteve.reinhardt@amd.com updateHandyM5Reg(regVal[MISCREG_EFER], 3717533Ssteve.reinhardt@amd.com regVal[MISCREG_CR0], 3727533Ssteve.reinhardt@amd.com regVal[MISCREG_CS_ATTR], 3737533Ssteve.reinhardt@amd.com regVal[MISCREG_SS_ATTR], 3749376Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS], 3759376Sgblack@eecs.umich.edu NULL); 3766313Sgblack@eecs.umich.edu} 3776313Sgblack@eecs.umich.edu 3786313Sgblack@eecs.umich.edu} 379