isa.cc revision 6336
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 316336Sgblack@eecs.umich.edu#include "arch/x86/floatregs.hh" 326313Sgblack@eecs.umich.edu#include "arch/x86/isa.hh" 336336Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 346336Sgblack@eecs.umich.edu#include "cpu/base.hh" 356313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 366336Sgblack@eecs.umich.edu#include "sim/serialize.hh" 376313Sgblack@eecs.umich.edu 386313Sgblack@eecs.umich.edunamespace X86ISA 396313Sgblack@eecs.umich.edu{ 406313Sgblack@eecs.umich.edu 416313Sgblack@eecs.umich.eduvoid 426336Sgblack@eecs.umich.eduISA::updateHandyM5Reg(Efer efer, CR0 cr0, 436336Sgblack@eecs.umich.edu SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) 446336Sgblack@eecs.umich.edu{ 456336Sgblack@eecs.umich.edu HandyM5Reg m5reg; 466336Sgblack@eecs.umich.edu if (efer.lma) { 476336Sgblack@eecs.umich.edu m5reg.mode = LongMode; 486336Sgblack@eecs.umich.edu if (csAttr.longMode) 496336Sgblack@eecs.umich.edu m5reg.submode = SixtyFourBitMode; 506336Sgblack@eecs.umich.edu else 516336Sgblack@eecs.umich.edu m5reg.submode = CompatabilityMode; 526336Sgblack@eecs.umich.edu } else { 536336Sgblack@eecs.umich.edu m5reg.mode = LegacyMode; 546336Sgblack@eecs.umich.edu if (cr0.pe) { 556336Sgblack@eecs.umich.edu if (rflags.vm) 566336Sgblack@eecs.umich.edu m5reg.submode = Virtual8086Mode; 576336Sgblack@eecs.umich.edu else 586336Sgblack@eecs.umich.edu m5reg.submode = ProtectedMode; 596336Sgblack@eecs.umich.edu } else { 606336Sgblack@eecs.umich.edu m5reg.submode = RealMode; 616336Sgblack@eecs.umich.edu } 626336Sgblack@eecs.umich.edu } 636336Sgblack@eecs.umich.edu m5reg.cpl = csAttr.dpl; 646336Sgblack@eecs.umich.edu m5reg.paging = cr0.pg; 656336Sgblack@eecs.umich.edu m5reg.prot = cr0.pe; 666336Sgblack@eecs.umich.edu 676336Sgblack@eecs.umich.edu // Compute the default and alternate operand size. 686336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 696336Sgblack@eecs.umich.edu m5reg.defOp = 2; 706336Sgblack@eecs.umich.edu m5reg.altOp = 1; 716336Sgblack@eecs.umich.edu } else { 726336Sgblack@eecs.umich.edu m5reg.defOp = 1; 736336Sgblack@eecs.umich.edu m5reg.altOp = 2; 746336Sgblack@eecs.umich.edu } 756336Sgblack@eecs.umich.edu 766336Sgblack@eecs.umich.edu // Compute the default and alternate address size. 776336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 786336Sgblack@eecs.umich.edu m5reg.defAddr = 3; 796336Sgblack@eecs.umich.edu m5reg.altAddr = 2; 806336Sgblack@eecs.umich.edu } else if (csAttr.defaultSize) { 816336Sgblack@eecs.umich.edu m5reg.defAddr = 2; 826336Sgblack@eecs.umich.edu m5reg.altAddr = 1; 836336Sgblack@eecs.umich.edu } else { 846336Sgblack@eecs.umich.edu m5reg.defAddr = 1; 856336Sgblack@eecs.umich.edu m5reg.altAddr = 2; 866336Sgblack@eecs.umich.edu } 876336Sgblack@eecs.umich.edu 886336Sgblack@eecs.umich.edu // Compute the stack size 896336Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 906336Sgblack@eecs.umich.edu m5reg.stack = 3; 916336Sgblack@eecs.umich.edu } else if (ssAttr.defaultSize) { 926336Sgblack@eecs.umich.edu m5reg.stack = 2; 936336Sgblack@eecs.umich.edu } else { 946336Sgblack@eecs.umich.edu m5reg.stack = 1; 956336Sgblack@eecs.umich.edu } 966336Sgblack@eecs.umich.edu 976336Sgblack@eecs.umich.edu regVal[MISCREG_M5_REG] = m5reg; 986336Sgblack@eecs.umich.edu} 996336Sgblack@eecs.umich.edu 1006336Sgblack@eecs.umich.eduvoid 1016313Sgblack@eecs.umich.eduISA::clear() 1026313Sgblack@eecs.umich.edu{ 1036336Sgblack@eecs.umich.edu // Blank everything. 0 might not be an appropriate value for some things, 1046336Sgblack@eecs.umich.edu // but it is for most. 1056336Sgblack@eecs.umich.edu memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 1066336Sgblack@eecs.umich.edu regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 1076336Sgblack@eecs.umich.edu regVal[MISCREG_DR7] = 1 << 10; 1086313Sgblack@eecs.umich.edu} 1096313Sgblack@eecs.umich.edu 1106313Sgblack@eecs.umich.eduMiscReg 1116313Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 1126313Sgblack@eecs.umich.edu{ 1136336Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 1146336Sgblack@eecs.umich.edu // Instructions should filter out these indexes, and nothing else should 1156336Sgblack@eecs.umich.edu // attempt to read them directly. 1166336Sgblack@eecs.umich.edu assert( miscReg != MISCREG_CR1 && 1176336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR4 && 1186336Sgblack@eecs.umich.edu miscReg < MISCREG_CR8) && 1196336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR8 && 1206336Sgblack@eecs.umich.edu miscReg <= MISCREG_CR15)); 1216336Sgblack@eecs.umich.edu 1226336Sgblack@eecs.umich.edu return regVal[miscReg]; 1236313Sgblack@eecs.umich.edu} 1246313Sgblack@eecs.umich.edu 1256313Sgblack@eecs.umich.eduMiscReg 1266336Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 1276313Sgblack@eecs.umich.edu{ 1286336Sgblack@eecs.umich.edu if (miscReg == MISCREG_TSC) { 1296336Sgblack@eecs.umich.edu return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 1306336Sgblack@eecs.umich.edu } 1316336Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 1326313Sgblack@eecs.umich.edu} 1336313Sgblack@eecs.umich.edu 1346313Sgblack@eecs.umich.eduvoid 1356336Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 1366313Sgblack@eecs.umich.edu{ 1376336Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 1386336Sgblack@eecs.umich.edu // Instructions should filter out these indexes, and nothing else should 1396336Sgblack@eecs.umich.edu // attempt to write to them directly. 1406336Sgblack@eecs.umich.edu assert( miscReg != MISCREG_CR1 && 1416336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR4 && 1426336Sgblack@eecs.umich.edu miscReg < MISCREG_CR8) && 1436336Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR8 && 1446336Sgblack@eecs.umich.edu miscReg <= MISCREG_CR15)); 1456336Sgblack@eecs.umich.edu regVal[miscReg] = val; 1466313Sgblack@eecs.umich.edu} 1476313Sgblack@eecs.umich.edu 1486313Sgblack@eecs.umich.eduvoid 1496336Sgblack@eecs.umich.eduISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 1506313Sgblack@eecs.umich.edu{ 1516336Sgblack@eecs.umich.edu MiscReg newVal = val; 1526336Sgblack@eecs.umich.edu switch(miscReg) 1536336Sgblack@eecs.umich.edu { 1546336Sgblack@eecs.umich.edu case MISCREG_CR0: 1556336Sgblack@eecs.umich.edu { 1566336Sgblack@eecs.umich.edu CR0 toggled = regVal[miscReg] ^ val; 1576336Sgblack@eecs.umich.edu CR0 newCR0 = val; 1586336Sgblack@eecs.umich.edu Efer efer = regVal[MISCREG_EFER]; 1596336Sgblack@eecs.umich.edu if (toggled.pg && efer.lme) { 1606336Sgblack@eecs.umich.edu if (newCR0.pg) { 1616336Sgblack@eecs.umich.edu //Turning on long mode 1626336Sgblack@eecs.umich.edu efer.lma = 1; 1636336Sgblack@eecs.umich.edu regVal[MISCREG_EFER] = efer; 1646336Sgblack@eecs.umich.edu } else { 1656336Sgblack@eecs.umich.edu //Turning off long mode 1666336Sgblack@eecs.umich.edu efer.lma = 0; 1676336Sgblack@eecs.umich.edu regVal[MISCREG_EFER] = efer; 1686336Sgblack@eecs.umich.edu } 1696336Sgblack@eecs.umich.edu } 1706336Sgblack@eecs.umich.edu if (toggled.pg) { 1716336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateAll(); 1726336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateAll(); 1736336Sgblack@eecs.umich.edu } 1746336Sgblack@eecs.umich.edu //This must always be 1. 1756336Sgblack@eecs.umich.edu newCR0.et = 1; 1766336Sgblack@eecs.umich.edu newVal = newCR0; 1776336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 1786336Sgblack@eecs.umich.edu newCR0, 1796336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 1806336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 1816336Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS]); 1826336Sgblack@eecs.umich.edu } 1836336Sgblack@eecs.umich.edu break; 1846336Sgblack@eecs.umich.edu case MISCREG_CR2: 1856336Sgblack@eecs.umich.edu break; 1866336Sgblack@eecs.umich.edu case MISCREG_CR3: 1876336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateNonGlobal(); 1886336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateNonGlobal(); 1896336Sgblack@eecs.umich.edu break; 1906336Sgblack@eecs.umich.edu case MISCREG_CR4: 1916336Sgblack@eecs.umich.edu { 1926336Sgblack@eecs.umich.edu CR4 toggled = regVal[miscReg] ^ val; 1936336Sgblack@eecs.umich.edu if (toggled.pae || toggled.pse || toggled.pge) { 1946336Sgblack@eecs.umich.edu tc->getITBPtr()->invalidateAll(); 1956336Sgblack@eecs.umich.edu tc->getDTBPtr()->invalidateAll(); 1966336Sgblack@eecs.umich.edu } 1976336Sgblack@eecs.umich.edu } 1986336Sgblack@eecs.umich.edu break; 1996336Sgblack@eecs.umich.edu case MISCREG_CR8: 2006336Sgblack@eecs.umich.edu break; 2016336Sgblack@eecs.umich.edu case MISCREG_CS_ATTR: 2026336Sgblack@eecs.umich.edu { 2036336Sgblack@eecs.umich.edu SegAttr toggled = regVal[miscReg] ^ val; 2046336Sgblack@eecs.umich.edu SegAttr newCSAttr = val; 2056336Sgblack@eecs.umich.edu if (toggled.longMode) { 2066336Sgblack@eecs.umich.edu if (newCSAttr.longMode) { 2076336Sgblack@eecs.umich.edu regVal[MISCREG_ES_EFF_BASE] = 0; 2086336Sgblack@eecs.umich.edu regVal[MISCREG_CS_EFF_BASE] = 0; 2096336Sgblack@eecs.umich.edu regVal[MISCREG_SS_EFF_BASE] = 0; 2106336Sgblack@eecs.umich.edu regVal[MISCREG_DS_EFF_BASE] = 0; 2116336Sgblack@eecs.umich.edu } else { 2126336Sgblack@eecs.umich.edu regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 2136336Sgblack@eecs.umich.edu regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 2146336Sgblack@eecs.umich.edu regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 2156336Sgblack@eecs.umich.edu regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 2166336Sgblack@eecs.umich.edu } 2176336Sgblack@eecs.umich.edu } 2186336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 2196336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 2206336Sgblack@eecs.umich.edu newCSAttr, 2216336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 2226336Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS]); 2236336Sgblack@eecs.umich.edu } 2246336Sgblack@eecs.umich.edu break; 2256336Sgblack@eecs.umich.edu case MISCREG_SS_ATTR: 2266336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 2276336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 2286336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 2296336Sgblack@eecs.umich.edu val, 2306336Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS]); 2316336Sgblack@eecs.umich.edu break; 2326336Sgblack@eecs.umich.edu // These segments always actually use their bases, or in other words 2336336Sgblack@eecs.umich.edu // their effective bases must stay equal to their actual bases. 2346336Sgblack@eecs.umich.edu case MISCREG_FS_BASE: 2356336Sgblack@eecs.umich.edu case MISCREG_GS_BASE: 2366336Sgblack@eecs.umich.edu case MISCREG_HS_BASE: 2376336Sgblack@eecs.umich.edu case MISCREG_TSL_BASE: 2386336Sgblack@eecs.umich.edu case MISCREG_TSG_BASE: 2396336Sgblack@eecs.umich.edu case MISCREG_TR_BASE: 2406336Sgblack@eecs.umich.edu case MISCREG_IDTR_BASE: 2416336Sgblack@eecs.umich.edu regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 2426336Sgblack@eecs.umich.edu break; 2436336Sgblack@eecs.umich.edu // These segments ignore their bases in 64 bit mode. 2446336Sgblack@eecs.umich.edu // their effective bases must stay equal to their actual bases. 2456336Sgblack@eecs.umich.edu case MISCREG_ES_BASE: 2466336Sgblack@eecs.umich.edu case MISCREG_CS_BASE: 2476336Sgblack@eecs.umich.edu case MISCREG_SS_BASE: 2486336Sgblack@eecs.umich.edu case MISCREG_DS_BASE: 2496336Sgblack@eecs.umich.edu { 2506336Sgblack@eecs.umich.edu Efer efer = regVal[MISCREG_EFER]; 2516336Sgblack@eecs.umich.edu SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 2526336Sgblack@eecs.umich.edu if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 2536336Sgblack@eecs.umich.edu regVal[MISCREG_SEG_EFF_BASE(miscReg - 2546336Sgblack@eecs.umich.edu MISCREG_SEG_BASE_BASE)] = val; 2556336Sgblack@eecs.umich.edu } 2566336Sgblack@eecs.umich.edu break; 2576336Sgblack@eecs.umich.edu case MISCREG_TSC: 2586336Sgblack@eecs.umich.edu regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 2596336Sgblack@eecs.umich.edu return; 2606336Sgblack@eecs.umich.edu case MISCREG_DR0: 2616336Sgblack@eecs.umich.edu case MISCREG_DR1: 2626336Sgblack@eecs.umich.edu case MISCREG_DR2: 2636336Sgblack@eecs.umich.edu case MISCREG_DR3: 2646336Sgblack@eecs.umich.edu /* These should eventually set up breakpoints. */ 2656336Sgblack@eecs.umich.edu break; 2666336Sgblack@eecs.umich.edu case MISCREG_DR4: 2676336Sgblack@eecs.umich.edu miscReg = MISCREG_DR6; 2686336Sgblack@eecs.umich.edu /* Fall through to have the same effects as DR6. */ 2696336Sgblack@eecs.umich.edu case MISCREG_DR6: 2706336Sgblack@eecs.umich.edu { 2716336Sgblack@eecs.umich.edu DR6 dr6 = regVal[MISCREG_DR6]; 2726336Sgblack@eecs.umich.edu DR6 newDR6 = val; 2736336Sgblack@eecs.umich.edu dr6.b0 = newDR6.b0; 2746336Sgblack@eecs.umich.edu dr6.b1 = newDR6.b1; 2756336Sgblack@eecs.umich.edu dr6.b2 = newDR6.b2; 2766336Sgblack@eecs.umich.edu dr6.b3 = newDR6.b3; 2776336Sgblack@eecs.umich.edu dr6.bd = newDR6.bd; 2786336Sgblack@eecs.umich.edu dr6.bs = newDR6.bs; 2796336Sgblack@eecs.umich.edu dr6.bt = newDR6.bt; 2806336Sgblack@eecs.umich.edu newVal = dr6; 2816336Sgblack@eecs.umich.edu } 2826336Sgblack@eecs.umich.edu break; 2836336Sgblack@eecs.umich.edu case MISCREG_DR5: 2846336Sgblack@eecs.umich.edu miscReg = MISCREG_DR7; 2856336Sgblack@eecs.umich.edu /* Fall through to have the same effects as DR7. */ 2866336Sgblack@eecs.umich.edu case MISCREG_DR7: 2876336Sgblack@eecs.umich.edu { 2886336Sgblack@eecs.umich.edu DR7 dr7 = regVal[MISCREG_DR7]; 2896336Sgblack@eecs.umich.edu DR7 newDR7 = val; 2906336Sgblack@eecs.umich.edu dr7.l0 = newDR7.l0; 2916336Sgblack@eecs.umich.edu dr7.g0 = newDR7.g0; 2926336Sgblack@eecs.umich.edu if (dr7.l0 || dr7.g0) { 2936336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 2946336Sgblack@eecs.umich.edu } else { 2956336Sgblack@eecs.umich.edu /* Disable breakpoint 0. */ 2966336Sgblack@eecs.umich.edu } 2976336Sgblack@eecs.umich.edu dr7.l1 = newDR7.l1; 2986336Sgblack@eecs.umich.edu dr7.g1 = newDR7.g1; 2996336Sgblack@eecs.umich.edu if (dr7.l1 || dr7.g1) { 3006336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3016336Sgblack@eecs.umich.edu } else { 3026336Sgblack@eecs.umich.edu /* Disable breakpoint 1. */ 3036336Sgblack@eecs.umich.edu } 3046336Sgblack@eecs.umich.edu dr7.l2 = newDR7.l2; 3056336Sgblack@eecs.umich.edu dr7.g2 = newDR7.g2; 3066336Sgblack@eecs.umich.edu if (dr7.l2 || dr7.g2) { 3076336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3086336Sgblack@eecs.umich.edu } else { 3096336Sgblack@eecs.umich.edu /* Disable breakpoint 2. */ 3106336Sgblack@eecs.umich.edu } 3116336Sgblack@eecs.umich.edu dr7.l3 = newDR7.l3; 3126336Sgblack@eecs.umich.edu dr7.g3 = newDR7.g3; 3136336Sgblack@eecs.umich.edu if (dr7.l3 || dr7.g3) { 3146336Sgblack@eecs.umich.edu panic("Debug register breakpoints not implemented.\n"); 3156336Sgblack@eecs.umich.edu } else { 3166336Sgblack@eecs.umich.edu /* Disable breakpoint 3. */ 3176336Sgblack@eecs.umich.edu } 3186336Sgblack@eecs.umich.edu dr7.gd = newDR7.gd; 3196336Sgblack@eecs.umich.edu dr7.rw0 = newDR7.rw0; 3206336Sgblack@eecs.umich.edu dr7.len0 = newDR7.len0; 3216336Sgblack@eecs.umich.edu dr7.rw1 = newDR7.rw1; 3226336Sgblack@eecs.umich.edu dr7.len1 = newDR7.len1; 3236336Sgblack@eecs.umich.edu dr7.rw2 = newDR7.rw2; 3246336Sgblack@eecs.umich.edu dr7.len2 = newDR7.len2; 3256336Sgblack@eecs.umich.edu dr7.rw3 = newDR7.rw3; 3266336Sgblack@eecs.umich.edu dr7.len3 = newDR7.len3; 3276336Sgblack@eecs.umich.edu } 3286336Sgblack@eecs.umich.edu break; 3296336Sgblack@eecs.umich.edu case MISCREG_M5_REG: 3306336Sgblack@eecs.umich.edu // Writing anything to the m5reg with side effects makes it update 3316336Sgblack@eecs.umich.edu // based on the current values of the relevant registers. The actual 3326336Sgblack@eecs.umich.edu // value written is discarded. 3336336Sgblack@eecs.umich.edu updateHandyM5Reg(regVal[MISCREG_EFER], 3346336Sgblack@eecs.umich.edu regVal[MISCREG_CR0], 3356336Sgblack@eecs.umich.edu regVal[MISCREG_CS_ATTR], 3366336Sgblack@eecs.umich.edu regVal[MISCREG_SS_ATTR], 3376336Sgblack@eecs.umich.edu regVal[MISCREG_RFLAGS]); 3386336Sgblack@eecs.umich.edu return; 3396336Sgblack@eecs.umich.edu default: 3406336Sgblack@eecs.umich.edu break; 3416336Sgblack@eecs.umich.edu } 3426336Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, newVal); 3436336Sgblack@eecs.umich.edu} 3446336Sgblack@eecs.umich.edu 3456336Sgblack@eecs.umich.eduvoid 3466336Sgblack@eecs.umich.eduISA::serialize(EventManager *em, std::ostream & os) 3476336Sgblack@eecs.umich.edu{ 3486336Sgblack@eecs.umich.edu SERIALIZE_ARRAY(regVal, NumMiscRegs); 3496336Sgblack@eecs.umich.edu} 3506336Sgblack@eecs.umich.edu 3516336Sgblack@eecs.umich.eduvoid 3526336Sgblack@eecs.umich.eduISA::unserialize(EventManager *em, Checkpoint * cp, 3536336Sgblack@eecs.umich.edu const std::string & section) 3546336Sgblack@eecs.umich.edu{ 3556336Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 3566313Sgblack@eecs.umich.edu} 3576313Sgblack@eecs.umich.edu 3586313Sgblack@eecs.umich.eduint 3596313Sgblack@eecs.umich.eduISA::flattenIntIndex(int reg) 3606313Sgblack@eecs.umich.edu{ 3616313Sgblack@eecs.umich.edu //If we need to fold over the index to match byte semantics, do that. 3626313Sgblack@eecs.umich.edu //Otherwise, just strip off any extra bits and pass it through. 3636313Sgblack@eecs.umich.edu if (reg & (1 << 6)) 3646313Sgblack@eecs.umich.edu return (reg & (~(1 << 6) - 0x4)); 3656313Sgblack@eecs.umich.edu else 3666313Sgblack@eecs.umich.edu return (reg & ~(1 << 6)); 3676313Sgblack@eecs.umich.edu} 3686313Sgblack@eecs.umich.edu 3696313Sgblack@eecs.umich.eduint 3706313Sgblack@eecs.umich.eduISA::flattenFloatIndex(int reg) 3716313Sgblack@eecs.umich.edu{ 3726313Sgblack@eecs.umich.edu if (reg >= NUM_FLOATREGS) { 3736336Sgblack@eecs.umich.edu int top = readMiscRegNoEffect(MISCREG_X87_TOP); 3746313Sgblack@eecs.umich.edu reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); 3756313Sgblack@eecs.umich.edu } 3766313Sgblack@eecs.umich.edu return reg; 3776313Sgblack@eecs.umich.edu} 3786313Sgblack@eecs.umich.edu 3796313Sgblack@eecs.umich.edu} 380