interrupts.cc revision 9524
15647Sgblack@eecs.umich.edu/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 145647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 155647Sgblack@eecs.umich.edu * All rights reserved. 165647Sgblack@eecs.umich.edu * 177087Snate@binkert.org * The license below extends only to copyright in the software and shall 187087Snate@binkert.org * not be construed as granting a license to any other intellectual 197087Snate@binkert.org * property including but not limited to intellectual property relating 207087Snate@binkert.org * to a hardware implementation of the functionality of the software 217087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 227087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 237087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 247087Snate@binkert.org * modified or unmodified, in source code or in binary form. 255647Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 277087Snate@binkert.org * modification, are permitted provided that the following conditions are 287087Snate@binkert.org * met: redistributions of source code must retain the above copyright 297087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 307087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 317087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 327087Snate@binkert.org * documentation and/or other materials provided with the distribution; 337087Snate@binkert.org * neither the name of the copyright holders nor the names of its 345647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 357087Snate@binkert.org * this software without specific prior written permission. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 385647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 395647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 405647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 415647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 425647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 435647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 445647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 455647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 465647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 475647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 485647Sgblack@eecs.umich.edu * 495647Sgblack@eecs.umich.edu * Authors: Gabe Black 505647Sgblack@eecs.umich.edu */ 515647Sgblack@eecs.umich.edu 528229Snate@binkert.org#include "arch/x86/regs/apic.hh" 535647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 545654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 555647Sgblack@eecs.umich.edu#include "cpu/base.hh" 568232Snate@binkert.org#include "debug/LocalApic.hh" 576137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 586137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 596137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 605654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 616046Sgblack@eecs.umich.edu#include "sim/system.hh" 628781Sgblack@eecs.umich.edu#include "sim/full_system.hh" 635647Sgblack@eecs.umich.edu 645648Sgblack@eecs.umich.eduint 655648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 665647Sgblack@eecs.umich.edu{ 675647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 685647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 695647Sgblack@eecs.umich.edu // be deciphered fairly easily. 705647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 715647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 725647Sgblack@eecs.umich.edu return 1 << shift; 735647Sgblack@eecs.umich.edu} 745647Sgblack@eecs.umich.edu 755648Sgblack@eecs.umich.edunamespace X86ISA 765647Sgblack@eecs.umich.edu{ 775648Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.eduApicRegIndex 795648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 805648Sgblack@eecs.umich.edu{ 815648Sgblack@eecs.umich.edu ApicRegIndex regNum; 825648Sgblack@eecs.umich.edu paddr &= ~mask(3); 835648Sgblack@eecs.umich.edu switch (paddr) 845648Sgblack@eecs.umich.edu { 855648Sgblack@eecs.umich.edu case 0x20: 865648Sgblack@eecs.umich.edu regNum = APIC_ID; 875648Sgblack@eecs.umich.edu break; 885648Sgblack@eecs.umich.edu case 0x30: 895648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 905648Sgblack@eecs.umich.edu break; 915648Sgblack@eecs.umich.edu case 0x80: 925648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 935648Sgblack@eecs.umich.edu break; 945648Sgblack@eecs.umich.edu case 0x90: 955648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 965648Sgblack@eecs.umich.edu break; 975648Sgblack@eecs.umich.edu case 0xA0: 985648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 995648Sgblack@eecs.umich.edu break; 1005648Sgblack@eecs.umich.edu case 0xB0: 1015648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1025648Sgblack@eecs.umich.edu break; 1035648Sgblack@eecs.umich.edu case 0xD0: 1045648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1055648Sgblack@eecs.umich.edu break; 1065648Sgblack@eecs.umich.edu case 0xE0: 1075648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1085648Sgblack@eecs.umich.edu break; 1095648Sgblack@eecs.umich.edu case 0xF0: 1105648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1115648Sgblack@eecs.umich.edu break; 1125648Sgblack@eecs.umich.edu case 0x100: 1135648Sgblack@eecs.umich.edu case 0x108: 1145648Sgblack@eecs.umich.edu case 0x110: 1155648Sgblack@eecs.umich.edu case 0x118: 1165648Sgblack@eecs.umich.edu case 0x120: 1175648Sgblack@eecs.umich.edu case 0x128: 1185648Sgblack@eecs.umich.edu case 0x130: 1195648Sgblack@eecs.umich.edu case 0x138: 1205648Sgblack@eecs.umich.edu case 0x140: 1215648Sgblack@eecs.umich.edu case 0x148: 1225648Sgblack@eecs.umich.edu case 0x150: 1235648Sgblack@eecs.umich.edu case 0x158: 1245648Sgblack@eecs.umich.edu case 0x160: 1255648Sgblack@eecs.umich.edu case 0x168: 1265648Sgblack@eecs.umich.edu case 0x170: 1275648Sgblack@eecs.umich.edu case 0x178: 1285648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1295648Sgblack@eecs.umich.edu break; 1305648Sgblack@eecs.umich.edu case 0x180: 1315648Sgblack@eecs.umich.edu case 0x188: 1325648Sgblack@eecs.umich.edu case 0x190: 1335648Sgblack@eecs.umich.edu case 0x198: 1345648Sgblack@eecs.umich.edu case 0x1A0: 1355648Sgblack@eecs.umich.edu case 0x1A8: 1365648Sgblack@eecs.umich.edu case 0x1B0: 1375648Sgblack@eecs.umich.edu case 0x1B8: 1385648Sgblack@eecs.umich.edu case 0x1C0: 1395648Sgblack@eecs.umich.edu case 0x1C8: 1405648Sgblack@eecs.umich.edu case 0x1D0: 1415648Sgblack@eecs.umich.edu case 0x1D8: 1425648Sgblack@eecs.umich.edu case 0x1E0: 1435648Sgblack@eecs.umich.edu case 0x1E8: 1445648Sgblack@eecs.umich.edu case 0x1F0: 1455648Sgblack@eecs.umich.edu case 0x1F8: 1465648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1475648Sgblack@eecs.umich.edu break; 1485648Sgblack@eecs.umich.edu case 0x200: 1495648Sgblack@eecs.umich.edu case 0x208: 1505648Sgblack@eecs.umich.edu case 0x210: 1515648Sgblack@eecs.umich.edu case 0x218: 1525648Sgblack@eecs.umich.edu case 0x220: 1535648Sgblack@eecs.umich.edu case 0x228: 1545648Sgblack@eecs.umich.edu case 0x230: 1555648Sgblack@eecs.umich.edu case 0x238: 1565648Sgblack@eecs.umich.edu case 0x240: 1575648Sgblack@eecs.umich.edu case 0x248: 1585648Sgblack@eecs.umich.edu case 0x250: 1595648Sgblack@eecs.umich.edu case 0x258: 1605648Sgblack@eecs.umich.edu case 0x260: 1615648Sgblack@eecs.umich.edu case 0x268: 1625648Sgblack@eecs.umich.edu case 0x270: 1635648Sgblack@eecs.umich.edu case 0x278: 1645648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1655648Sgblack@eecs.umich.edu break; 1665648Sgblack@eecs.umich.edu case 0x280: 1675648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1685648Sgblack@eecs.umich.edu break; 1695648Sgblack@eecs.umich.edu case 0x300: 1705648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1715648Sgblack@eecs.umich.edu break; 1725648Sgblack@eecs.umich.edu case 0x310: 1735648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1745648Sgblack@eecs.umich.edu break; 1755648Sgblack@eecs.umich.edu case 0x320: 1765648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1775648Sgblack@eecs.umich.edu break; 1785648Sgblack@eecs.umich.edu case 0x330: 1795648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1805648Sgblack@eecs.umich.edu break; 1815648Sgblack@eecs.umich.edu case 0x340: 1825648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1835648Sgblack@eecs.umich.edu break; 1845648Sgblack@eecs.umich.edu case 0x350: 1855648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1865648Sgblack@eecs.umich.edu break; 1875648Sgblack@eecs.umich.edu case 0x360: 1885648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1895648Sgblack@eecs.umich.edu break; 1905648Sgblack@eecs.umich.edu case 0x370: 1915648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1925648Sgblack@eecs.umich.edu break; 1935648Sgblack@eecs.umich.edu case 0x380: 1945648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1955648Sgblack@eecs.umich.edu break; 1965648Sgblack@eecs.umich.edu case 0x390: 1975648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1985648Sgblack@eecs.umich.edu break; 1995648Sgblack@eecs.umich.edu case 0x3E0: 2005648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2015648Sgblack@eecs.umich.edu break; 2025648Sgblack@eecs.umich.edu default: 2035648Sgblack@eecs.umich.edu // A reserved register field. 2045648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2055648Sgblack@eecs.umich.edu break; 2065648Sgblack@eecs.umich.edu } 2075648Sgblack@eecs.umich.edu return regNum; 2085648Sgblack@eecs.umich.edu} 2095648Sgblack@eecs.umich.edu} 2105648Sgblack@eecs.umich.edu 2115648Sgblack@eecs.umich.eduTick 2125648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2135648Sgblack@eecs.umich.edu{ 2145648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2155648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2165648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2175648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2185648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2195648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2205649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2215649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2225649Sgblack@eecs.umich.edu reg, offset, val); 2235648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2245898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2255648Sgblack@eecs.umich.edu return latency; 2265648Sgblack@eecs.umich.edu} 2275648Sgblack@eecs.umich.edu 2285648Sgblack@eecs.umich.eduTick 2295648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2305648Sgblack@eecs.umich.edu{ 2315648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2325648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2335648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2345648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2355648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2365648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2375648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2385649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2395649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2405649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2415648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2425898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2435648Sgblack@eecs.umich.edu return latency; 2445647Sgblack@eecs.umich.edu} 2455691Sgblack@eecs.umich.eduvoid 2465691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2475691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2485691Sgblack@eecs.umich.edu{ 2495691Sgblack@eecs.umich.edu /* 2505691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2515691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2525691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2535691Sgblack@eecs.umich.edu */ 2545691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2555691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2565691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2575691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2585691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2595691Sgblack@eecs.umich.edu if (vector > IRRV) 2605691Sgblack@eecs.umich.edu IRRV = vector; 2615691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2625691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2635691Sgblack@eecs.umich.edu if (level) { 2645691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2655691Sgblack@eecs.umich.edu } else { 2665691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2675691Sgblack@eecs.umich.edu } 2685691Sgblack@eecs.umich.edu } 2695691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2705691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2715691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2725691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2735691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2745691Sgblack@eecs.umich.edu smiVector = vector; 2755691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2765691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2775691Sgblack@eecs.umich.edu nmiVector = vector; 2785691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2795691Sgblack@eecs.umich.edu pendingExtInt = true; 2805691Sgblack@eecs.umich.edu extIntVector = vector; 2815691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2825691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2835691Sgblack@eecs.umich.edu initVector = vector; 2846066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2856066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2866050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2876050Sgblack@eecs.umich.edu startupVector = vector; 2885691Sgblack@eecs.umich.edu } 2898745Sgblack@eecs.umich.edu } 2908781Sgblack@eecs.umich.edu if (FullSystem) 2918781Sgblack@eecs.umich.edu cpu->wakeup(); 2925691Sgblack@eecs.umich.edu} 2935647Sgblack@eecs.umich.edu 2946041Sgblack@eecs.umich.edu 2956041Sgblack@eecs.umich.eduvoid 2966041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2976041Sgblack@eecs.umich.edu{ 2986136Sgblack@eecs.umich.edu assert(newCPU); 2996136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 3006136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 3016136Sgblack@eecs.umich.edu " with different IDs.\n"); 3026136Sgblack@eecs.umich.edu } 3036041Sgblack@eecs.umich.edu cpu = newCPU; 3046136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 3056136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 3069090Sandreas.hansson@arm.com pioAddr = x86LocalAPICAddress(initialApicId, 0); 3076041Sgblack@eecs.umich.edu} 3086041Sgblack@eecs.umich.edu 3096041Sgblack@eecs.umich.edu 3106137Sgblack@eecs.umich.eduvoid 3116137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 3126137Sgblack@eecs.umich.edu{ 3137913SBrad.Beckmann@amd.com // 3147913SBrad.Beckmann@amd.com // The local apic must register its address ranges on both its pio port 3157913SBrad.Beckmann@amd.com // via the basicpiodevice(piodevice) init() function and its int port 3167913SBrad.Beckmann@amd.com // that it inherited from IntDev. Note IntDev is not a SimObject itself. 3177913SBrad.Beckmann@amd.com // 3186137Sgblack@eecs.umich.edu BasicPioDevice::init(); 3197913SBrad.Beckmann@amd.com IntDev::init(); 3208922Swilliam.wang@arm.com 3218922Swilliam.wang@arm.com // the slave port has a range so inform the connected master 3228922Swilliam.wang@arm.com intSlavePort.sendRangeChange(); 3236137Sgblack@eecs.umich.edu} 3246137Sgblack@eecs.umich.edu 3256137Sgblack@eecs.umich.edu 3265651Sgblack@eecs.umich.eduTick 3275651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3285651Sgblack@eecs.umich.edu{ 3296136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3305651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3315651Sgblack@eecs.umich.edu switch(offset) 3325651Sgblack@eecs.umich.edu { 3335651Sgblack@eecs.umich.edu case 0: 3345654Sgblack@eecs.umich.edu { 3355654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3365654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3375654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3385697Snate@binkert.org message.vector); 3395655Sgblack@eecs.umich.edu 3405691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3415691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3425654Sgblack@eecs.umich.edu } 3435651Sgblack@eecs.umich.edu break; 3445651Sgblack@eecs.umich.edu default: 3455651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3465651Sgblack@eecs.umich.edu offset); 3475651Sgblack@eecs.umich.edu break; 3485651Sgblack@eecs.umich.edu } 3496064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3505651Sgblack@eecs.umich.edu return latency; 3515651Sgblack@eecs.umich.edu} 3525651Sgblack@eecs.umich.edu 3535651Sgblack@eecs.umich.edu 3546065Sgblack@eecs.umich.eduTick 3556065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3566065Sgblack@eecs.umich.edu{ 3576065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3586065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3596069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3606069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3616069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3626069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3636069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3646069Sgblack@eecs.umich.edu } 3656065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3666065Sgblack@eecs.umich.edu return 0; 3676065Sgblack@eecs.umich.edu} 3686065Sgblack@eecs.umich.edu 3696065Sgblack@eecs.umich.edu 3708711Sandreas.hansson@arm.comAddrRangeList 3719090Sandreas.hansson@arm.comX86ISA::Interrupts::getAddrRanges() const 3726041Sgblack@eecs.umich.edu{ 3738711Sandreas.hansson@arm.com AddrRangeList ranges; 3749235Sandreas.hansson@arm.com AddrRange range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3759235Sandreas.hansson@arm.com x86LocalAPICAddress(initialApicId, 0) + 3769235Sandreas.hansson@arm.com PageBytes); 3778711Sandreas.hansson@arm.com ranges.push_back(range); 3788711Sandreas.hansson@arm.com return ranges; 3796041Sgblack@eecs.umich.edu} 3806041Sgblack@eecs.umich.edu 3816041Sgblack@eecs.umich.edu 3828711Sandreas.hansson@arm.comAddrRangeList 3839090Sandreas.hansson@arm.comX86ISA::Interrupts::getIntAddrRange() const 3846041Sgblack@eecs.umich.edu{ 3858711Sandreas.hansson@arm.com AddrRangeList ranges; 3868711Sandreas.hansson@arm.com ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3878711Sandreas.hansson@arm.com x86InterruptAddress(initialApicId, 0) + 3888711Sandreas.hansson@arm.com PhysAddrAPICRangeSize)); 3898711Sandreas.hansson@arm.com return ranges; 3906041Sgblack@eecs.umich.edu} 3916041Sgblack@eecs.umich.edu 3926041Sgblack@eecs.umich.edu 3935647Sgblack@eecs.umich.eduuint32_t 3945648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3955647Sgblack@eecs.umich.edu{ 3965647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3975647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3985647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3995647Sgblack@eecs.umich.edu } 4005647Sgblack@eecs.umich.edu switch (reg) { 4015647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4025647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4035647Sgblack@eecs.umich.edu break; 4045647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4055647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4065647Sgblack@eecs.umich.edu break; 4075647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4085647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4095647Sgblack@eecs.umich.edu break; 4105647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 4115647Sgblack@eecs.umich.edu { 4125848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 4135848Sgblack@eecs.umich.edu assert(clock); 4145848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 4155848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 4165848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 4175848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 4187823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 4195848Sgblack@eecs.umich.edu // Turn that into a count. 4205848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 4215848Sgblack@eecs.umich.edu return val; 4225848Sgblack@eecs.umich.edu } else { 4235848Sgblack@eecs.umich.edu return 0; 4245848Sgblack@eecs.umich.edu } 4255647Sgblack@eecs.umich.edu } 4265647Sgblack@eecs.umich.edu default: 4275647Sgblack@eecs.umich.edu break; 4285647Sgblack@eecs.umich.edu } 4295648Sgblack@eecs.umich.edu return regs[reg]; 4305647Sgblack@eecs.umich.edu} 4315647Sgblack@eecs.umich.edu 4325647Sgblack@eecs.umich.eduvoid 4335648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4345647Sgblack@eecs.umich.edu{ 4355647Sgblack@eecs.umich.edu uint32_t newVal = val; 4365647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4375647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4385647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4395647Sgblack@eecs.umich.edu } 4405647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4415647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4425647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4435647Sgblack@eecs.umich.edu } 4445647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4455647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4465647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4475647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4485647Sgblack@eecs.umich.edu } 4495647Sgblack@eecs.umich.edu switch (reg) { 4505647Sgblack@eecs.umich.edu case APIC_ID: 4515647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4525647Sgblack@eecs.umich.edu break; 4535647Sgblack@eecs.umich.edu case APIC_VERSION: 4545647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4555647Sgblack@eecs.umich.edu return; 4565647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4575647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4605647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4615647Sgblack@eecs.umich.edu break; 4625647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4635647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4645647Sgblack@eecs.umich.edu break; 4655647Sgblack@eecs.umich.edu case APIC_EOI: 4665690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4675690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4685690Sgblack@eecs.umich.edu updateISRV(); 4695690Sgblack@eecs.umich.edu return; 4705647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4715647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4725647Sgblack@eecs.umich.edu break; 4735647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4745647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4755647Sgblack@eecs.umich.edu break; 4765647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4775647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4785647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4795647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4805647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4815647Sgblack@eecs.umich.edu break; 4825647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4835647Sgblack@eecs.umich.edu { 4845647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4855647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4865647Sgblack@eecs.umich.edu newVal = 0; 4875647Sgblack@eecs.umich.edu } else { 4885647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4895647Sgblack@eecs.umich.edu return; 4905647Sgblack@eecs.umich.edu } 4915647Sgblack@eecs.umich.edu 4925647Sgblack@eecs.umich.edu } 4935647Sgblack@eecs.umich.edu break; 4945647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4956046Sgblack@eecs.umich.edu { 4966046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4976046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4986046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4996046Sgblack@eecs.umich.edu newVal = low; 5006046Sgblack@eecs.umich.edu break; 5016046Sgblack@eecs.umich.edu } 5026046Sgblack@eecs.umich.edu low = val; 5036046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 5046046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 5056046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 5066712Snate@binkert.org TriggerIntMessage message = 0; 5076046Sgblack@eecs.umich.edu message.destination = high.destination; 5086046Sgblack@eecs.umich.edu message.vector = low.vector; 5096046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 5106046Sgblack@eecs.umich.edu message.destMode = low.destMode; 5116046Sgblack@eecs.umich.edu message.level = low.level; 5126046Sgblack@eecs.umich.edu message.trigger = low.trigger; 5139524SAndreas.Sandberg@ARM.com bool timing(sys->isTimingMode()); 5146065Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 5156065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 5166138Sgblack@eecs.umich.edu ApicList apics; 5176138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 5186046Sgblack@eecs.umich.edu switch (low.destShorthand) { 5196046Sgblack@eecs.umich.edu case 0: 5206138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 5216138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 5226138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 5236138Sgblack@eecs.umich.edu } 5246138Sgblack@eecs.umich.edu if (message.destMode == 1) { 5256138Sgblack@eecs.umich.edu int dest = message.destination; 5266138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 5276138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5286138Sgblack@eecs.umich.edu if (dest & 0x1) 5296138Sgblack@eecs.umich.edu apics.push_back(i); 5306138Sgblack@eecs.umich.edu dest = dest >> 1; 5316138Sgblack@eecs.umich.edu } 5326138Sgblack@eecs.umich.edu } else { 5336138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5346138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5356138Sgblack@eecs.umich.edu if (i == initialApicId) { 5366138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5376138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5386138Sgblack@eecs.umich.edu } else { 5396138Sgblack@eecs.umich.edu apics.push_back(i); 5406138Sgblack@eecs.umich.edu } 5416138Sgblack@eecs.umich.edu } 5426138Sgblack@eecs.umich.edu } else { 5436138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5446138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5456138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5466138Sgblack@eecs.umich.edu } else { 5476138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5486138Sgblack@eecs.umich.edu } 5496138Sgblack@eecs.umich.edu } 5506138Sgblack@eecs.umich.edu } 5516046Sgblack@eecs.umich.edu break; 5526046Sgblack@eecs.umich.edu case 1: 5536069Sgblack@eecs.umich.edu newVal = val; 5546069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5556069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5566046Sgblack@eecs.umich.edu break; 5576046Sgblack@eecs.umich.edu case 2: 5586069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5596069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5606069Sgblack@eecs.umich.edu // Fall through 5616046Sgblack@eecs.umich.edu case 3: 5626069Sgblack@eecs.umich.edu { 5636069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5646138Sgblack@eecs.umich.edu if (i != initialApicId) { 5656138Sgblack@eecs.umich.edu apics.push_back(i); 5666069Sgblack@eecs.umich.edu } 5676069Sgblack@eecs.umich.edu } 5686069Sgblack@eecs.umich.edu } 5696046Sgblack@eecs.umich.edu break; 5706046Sgblack@eecs.umich.edu } 5716138Sgblack@eecs.umich.edu pendingIPIs += apics.size(); 5728922Swilliam.wang@arm.com intMasterPort.sendMessage(apics, message, timing); 5736138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5746046Sgblack@eecs.umich.edu } 5755647Sgblack@eecs.umich.edu break; 5765647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5775647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5785647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5795647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5805647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5815647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5825647Sgblack@eecs.umich.edu { 5835647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5845647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5855647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5865647Sgblack@eecs.umich.edu } 5875647Sgblack@eecs.umich.edu break; 5885647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5895648Sgblack@eecs.umich.edu { 5905648Sgblack@eecs.umich.edu assert(clock); 5915648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5925848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5935848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5945848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5955648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5967823Ssteve.reinhardt@amd.com Tick offset = curTick() % clock; 5975648Sgblack@eecs.umich.edu if (offset) { 5985648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5997823Ssteve.reinhardt@amd.com curTick() + (newCount + 1) * clock - offset, true); 6005648Sgblack@eecs.umich.edu } else { 6015648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 6027823Ssteve.reinhardt@amd.com curTick() + newCount * clock, true); 6035648Sgblack@eecs.umich.edu } 6045648Sgblack@eecs.umich.edu } 6055647Sgblack@eecs.umich.edu break; 6065647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 6075647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 6085647Sgblack@eecs.umich.edu return; 6095647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 6105647Sgblack@eecs.umich.edu newVal = val & 0xB; 6115647Sgblack@eecs.umich.edu break; 6125647Sgblack@eecs.umich.edu default: 6135647Sgblack@eecs.umich.edu break; 6145647Sgblack@eecs.umich.edu } 6155648Sgblack@eecs.umich.edu regs[reg] = newVal; 6165647Sgblack@eecs.umich.edu return; 6175647Sgblack@eecs.umich.edu} 6185647Sgblack@eecs.umich.edu 6196041Sgblack@eecs.umich.edu 6206041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 6217900Shestness@cs.utexas.edu BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 6226041Sgblack@eecs.umich.edu apicTimerEvent(this), 6236041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 6246041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 6256041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 6266041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 6276050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 6286069Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 6298851Sandreas.hansson@arm.com pendingIPIs(0), cpu(NULL), 6308851Sandreas.hansson@arm.com intSlavePort(name() + ".int_slave", this, this, latency) 6316041Sgblack@eecs.umich.edu{ 6329157Sandreas.hansson@arm.com // Override the default clock 6339157Sandreas.hansson@arm.com clock = 0; 6346041Sgblack@eecs.umich.edu pioSize = PageBytes; 6356041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6366041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6376041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6386041Sgblack@eecs.umich.edu ISRV = 0; 6396041Sgblack@eecs.umich.edu IRRV = 0; 6406041Sgblack@eecs.umich.edu} 6416041Sgblack@eecs.umich.edu 6426041Sgblack@eecs.umich.edu 6435654Sgblack@eecs.umich.edubool 6445704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6455654Sgblack@eecs.umich.edu{ 6465654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6475689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6485689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6495654Sgblack@eecs.umich.edu return true; 6505689Sgblack@eecs.umich.edu } 6515655Sgblack@eecs.umich.edu if (rflags.intf) { 6525689Sgblack@eecs.umich.edu if (pendingExtInt) { 6535689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6545655Sgblack@eecs.umich.edu return true; 6555689Sgblack@eecs.umich.edu } 6565655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6575689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6585689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6595655Sgblack@eecs.umich.edu return true; 6605689Sgblack@eecs.umich.edu } 6615654Sgblack@eecs.umich.edu } 6625654Sgblack@eecs.umich.edu return false; 6635654Sgblack@eecs.umich.edu} 6645654Sgblack@eecs.umich.edu 6655654Sgblack@eecs.umich.eduFault 6665704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6675654Sgblack@eecs.umich.edu{ 6685704Snate@binkert.org assert(checkInterrupts(tc)); 6695655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6705655Sgblack@eecs.umich.edu // check for. 6715655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6725655Sgblack@eecs.umich.edu if (pendingSmi) { 6735689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6745655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6755655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6765689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6775691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6785655Sgblack@eecs.umich.edu } else if (pendingInit) { 6795689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6805691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6816050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6826050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6836050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6845655Sgblack@eecs.umich.edu } else { 6855655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6865655Sgblack@eecs.umich.edu "ints were pending.\n"); 6875655Sgblack@eecs.umich.edu return NoFault; 6885655Sgblack@eecs.umich.edu } 6895655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6905689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6915691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6925655Sgblack@eecs.umich.edu } else { 6935689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6945655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6955655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6965655Sgblack@eecs.umich.edu } 6975654Sgblack@eecs.umich.edu} 6985654Sgblack@eecs.umich.edu 6995654Sgblack@eecs.umich.eduvoid 7005704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 7015654Sgblack@eecs.umich.edu{ 7025704Snate@binkert.org assert(checkInterrupts(tc)); 7035655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 7045655Sgblack@eecs.umich.edu if (pendingSmi) { 7055689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 7065655Sgblack@eecs.umich.edu pendingSmi = false; 7075655Sgblack@eecs.umich.edu } else if (pendingNmi) { 7085689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 7095655Sgblack@eecs.umich.edu pendingNmi = false; 7105655Sgblack@eecs.umich.edu } else if (pendingInit) { 7115689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 7125655Sgblack@eecs.umich.edu pendingInit = false; 7136066Sgblack@eecs.umich.edu startedUp = false; 7146050Sgblack@eecs.umich.edu } else if (pendingStartup) { 7156050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 7166050Sgblack@eecs.umich.edu pendingStartup = false; 7176066Sgblack@eecs.umich.edu startedUp = true; 7185655Sgblack@eecs.umich.edu } 7196050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 7205655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 7215655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 7225655Sgblack@eecs.umich.edu pendingExtInt = false; 7235655Sgblack@eecs.umich.edu } else { 7245689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7255655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7265655Sgblack@eecs.umich.edu ISRV = IRRV; 7275655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7285655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7295655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7305655Sgblack@eecs.umich.edu updateIRRV(); 7315655Sgblack@eecs.umich.edu } 7325654Sgblack@eecs.umich.edu} 7335654Sgblack@eecs.umich.edu 7347902Shestness@cs.utexas.eduvoid 7357902Shestness@cs.utexas.eduX86ISA::Interrupts::serialize(std::ostream &os) 7367902Shestness@cs.utexas.edu{ 7377902Shestness@cs.utexas.edu SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7387902Shestness@cs.utexas.edu SERIALIZE_SCALAR(clock); 7397902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingSmi); 7407902Shestness@cs.utexas.edu SERIALIZE_SCALAR(smiVector); 7417902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingNmi); 7427902Shestness@cs.utexas.edu SERIALIZE_SCALAR(nmiVector); 7437902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingExtInt); 7447902Shestness@cs.utexas.edu SERIALIZE_SCALAR(extIntVector); 7457902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingInit); 7467902Shestness@cs.utexas.edu SERIALIZE_SCALAR(initVector); 7477902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingStartup); 7487902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startupVector); 7497902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startedUp); 7507902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingUnmaskableInt); 7517902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingIPIs); 7527902Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRRV); 7537902Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISRV); 7547902Shestness@cs.utexas.edu bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 7557902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventScheduled); 7567902Shestness@cs.utexas.edu Tick apicTimerEventTick = apicTimerEvent.when(); 7577902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventTick); 7587902Shestness@cs.utexas.edu} 7597902Shestness@cs.utexas.edu 7607902Shestness@cs.utexas.eduvoid 7617902Shestness@cs.utexas.eduX86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 7627902Shestness@cs.utexas.edu{ 7637902Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7647902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(clock); 7657902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingSmi); 7667902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(smiVector); 7677902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingNmi); 7687902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(nmiVector); 7697902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingExtInt); 7707902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(extIntVector); 7717902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingInit); 7727902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initVector); 7737902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingStartup); 7747902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startupVector); 7757902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startedUp); 7767902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingUnmaskableInt); 7777902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingIPIs); 7787902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRRV); 7797902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISRV); 7807902Shestness@cs.utexas.edu bool apicTimerEventScheduled; 7817902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventScheduled); 7827902Shestness@cs.utexas.edu if (apicTimerEventScheduled) { 7837902Shestness@cs.utexas.edu Tick apicTimerEventTick; 7847902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventTick); 7857902Shestness@cs.utexas.edu if (apicTimerEvent.scheduled()) { 7867902Shestness@cs.utexas.edu reschedule(apicTimerEvent, apicTimerEventTick, true); 7877902Shestness@cs.utexas.edu } else { 7887902Shestness@cs.utexas.edu schedule(apicTimerEvent, apicTimerEventTick); 7897902Shestness@cs.utexas.edu } 7907902Shestness@cs.utexas.edu } 7917902Shestness@cs.utexas.edu} 7927902Shestness@cs.utexas.edu 7935647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7945647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7955647Sgblack@eecs.umich.edu{ 7965647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7975647Sgblack@eecs.umich.edu} 798