interrupts.cc revision 8742
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135647Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 225647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 245647Sgblack@eecs.umich.edu * 255647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * Authors: Gabe Black 385647Sgblack@eecs.umich.edu */ 395647Sgblack@eecs.umich.edu 408229Snate@binkert.org#include "arch/x86/regs/apic.hh" 415647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 425654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 435647Sgblack@eecs.umich.edu#include "cpu/base.hh" 448232Snate@binkert.org#include "debug/LocalApic.hh" 456137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 466137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 476137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 485654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 496046Sgblack@eecs.umich.edu#include "sim/system.hh" 505647Sgblack@eecs.umich.edu 515648Sgblack@eecs.umich.eduint 525648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 535647Sgblack@eecs.umich.edu{ 545647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 555647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 565647Sgblack@eecs.umich.edu // be deciphered fairly easily. 575647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 585647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 595647Sgblack@eecs.umich.edu return 1 << shift; 605647Sgblack@eecs.umich.edu} 615647Sgblack@eecs.umich.edu 625648Sgblack@eecs.umich.edunamespace X86ISA 635647Sgblack@eecs.umich.edu{ 645648Sgblack@eecs.umich.edu 655648Sgblack@eecs.umich.eduApicRegIndex 665648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 675648Sgblack@eecs.umich.edu{ 685648Sgblack@eecs.umich.edu ApicRegIndex regNum; 695648Sgblack@eecs.umich.edu paddr &= ~mask(3); 705648Sgblack@eecs.umich.edu switch (paddr) 715648Sgblack@eecs.umich.edu { 725648Sgblack@eecs.umich.edu case 0x20: 735648Sgblack@eecs.umich.edu regNum = APIC_ID; 745648Sgblack@eecs.umich.edu break; 755648Sgblack@eecs.umich.edu case 0x30: 765648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 775648Sgblack@eecs.umich.edu break; 785648Sgblack@eecs.umich.edu case 0x80: 795648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 805648Sgblack@eecs.umich.edu break; 815648Sgblack@eecs.umich.edu case 0x90: 825648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 835648Sgblack@eecs.umich.edu break; 845648Sgblack@eecs.umich.edu case 0xA0: 855648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 865648Sgblack@eecs.umich.edu break; 875648Sgblack@eecs.umich.edu case 0xB0: 885648Sgblack@eecs.umich.edu regNum = APIC_EOI; 895648Sgblack@eecs.umich.edu break; 905648Sgblack@eecs.umich.edu case 0xD0: 915648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 925648Sgblack@eecs.umich.edu break; 935648Sgblack@eecs.umich.edu case 0xE0: 945648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 955648Sgblack@eecs.umich.edu break; 965648Sgblack@eecs.umich.edu case 0xF0: 975648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 985648Sgblack@eecs.umich.edu break; 995648Sgblack@eecs.umich.edu case 0x100: 1005648Sgblack@eecs.umich.edu case 0x108: 1015648Sgblack@eecs.umich.edu case 0x110: 1025648Sgblack@eecs.umich.edu case 0x118: 1035648Sgblack@eecs.umich.edu case 0x120: 1045648Sgblack@eecs.umich.edu case 0x128: 1055648Sgblack@eecs.umich.edu case 0x130: 1065648Sgblack@eecs.umich.edu case 0x138: 1075648Sgblack@eecs.umich.edu case 0x140: 1085648Sgblack@eecs.umich.edu case 0x148: 1095648Sgblack@eecs.umich.edu case 0x150: 1105648Sgblack@eecs.umich.edu case 0x158: 1115648Sgblack@eecs.umich.edu case 0x160: 1125648Sgblack@eecs.umich.edu case 0x168: 1135648Sgblack@eecs.umich.edu case 0x170: 1145648Sgblack@eecs.umich.edu case 0x178: 1155648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1165648Sgblack@eecs.umich.edu break; 1175648Sgblack@eecs.umich.edu case 0x180: 1185648Sgblack@eecs.umich.edu case 0x188: 1195648Sgblack@eecs.umich.edu case 0x190: 1205648Sgblack@eecs.umich.edu case 0x198: 1215648Sgblack@eecs.umich.edu case 0x1A0: 1225648Sgblack@eecs.umich.edu case 0x1A8: 1235648Sgblack@eecs.umich.edu case 0x1B0: 1245648Sgblack@eecs.umich.edu case 0x1B8: 1255648Sgblack@eecs.umich.edu case 0x1C0: 1265648Sgblack@eecs.umich.edu case 0x1C8: 1275648Sgblack@eecs.umich.edu case 0x1D0: 1285648Sgblack@eecs.umich.edu case 0x1D8: 1295648Sgblack@eecs.umich.edu case 0x1E0: 1305648Sgblack@eecs.umich.edu case 0x1E8: 1315648Sgblack@eecs.umich.edu case 0x1F0: 1325648Sgblack@eecs.umich.edu case 0x1F8: 1335648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1345648Sgblack@eecs.umich.edu break; 1355648Sgblack@eecs.umich.edu case 0x200: 1365648Sgblack@eecs.umich.edu case 0x208: 1375648Sgblack@eecs.umich.edu case 0x210: 1385648Sgblack@eecs.umich.edu case 0x218: 1395648Sgblack@eecs.umich.edu case 0x220: 1405648Sgblack@eecs.umich.edu case 0x228: 1415648Sgblack@eecs.umich.edu case 0x230: 1425648Sgblack@eecs.umich.edu case 0x238: 1435648Sgblack@eecs.umich.edu case 0x240: 1445648Sgblack@eecs.umich.edu case 0x248: 1455648Sgblack@eecs.umich.edu case 0x250: 1465648Sgblack@eecs.umich.edu case 0x258: 1475648Sgblack@eecs.umich.edu case 0x260: 1485648Sgblack@eecs.umich.edu case 0x268: 1495648Sgblack@eecs.umich.edu case 0x270: 1505648Sgblack@eecs.umich.edu case 0x278: 1515648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1525648Sgblack@eecs.umich.edu break; 1535648Sgblack@eecs.umich.edu case 0x280: 1545648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1555648Sgblack@eecs.umich.edu break; 1565648Sgblack@eecs.umich.edu case 0x300: 1575648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1585648Sgblack@eecs.umich.edu break; 1595648Sgblack@eecs.umich.edu case 0x310: 1605648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1615648Sgblack@eecs.umich.edu break; 1625648Sgblack@eecs.umich.edu case 0x320: 1635648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1645648Sgblack@eecs.umich.edu break; 1655648Sgblack@eecs.umich.edu case 0x330: 1665648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1675648Sgblack@eecs.umich.edu break; 1685648Sgblack@eecs.umich.edu case 0x340: 1695648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1705648Sgblack@eecs.umich.edu break; 1715648Sgblack@eecs.umich.edu case 0x350: 1725648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1735648Sgblack@eecs.umich.edu break; 1745648Sgblack@eecs.umich.edu case 0x360: 1755648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1765648Sgblack@eecs.umich.edu break; 1775648Sgblack@eecs.umich.edu case 0x370: 1785648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1795648Sgblack@eecs.umich.edu break; 1805648Sgblack@eecs.umich.edu case 0x380: 1815648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1825648Sgblack@eecs.umich.edu break; 1835648Sgblack@eecs.umich.edu case 0x390: 1845648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1855648Sgblack@eecs.umich.edu break; 1865648Sgblack@eecs.umich.edu case 0x3E0: 1875648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 1885648Sgblack@eecs.umich.edu break; 1895648Sgblack@eecs.umich.edu default: 1905648Sgblack@eecs.umich.edu // A reserved register field. 1915648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 1925648Sgblack@eecs.umich.edu break; 1935648Sgblack@eecs.umich.edu } 1945648Sgblack@eecs.umich.edu return regNum; 1955648Sgblack@eecs.umich.edu} 1965648Sgblack@eecs.umich.edu} 1975648Sgblack@eecs.umich.edu 1985648Sgblack@eecs.umich.eduTick 1995648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2005648Sgblack@eecs.umich.edu{ 2015648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2025648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2035648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2045648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2055648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2065648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2075649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2085649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2095649Sgblack@eecs.umich.edu reg, offset, val); 2105648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2115898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2125648Sgblack@eecs.umich.edu return latency; 2135648Sgblack@eecs.umich.edu} 2145648Sgblack@eecs.umich.edu 2155648Sgblack@eecs.umich.eduTick 2165648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2175648Sgblack@eecs.umich.edu{ 2185648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2195648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2205648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2215648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2225648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2235648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2245648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2255649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2265649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2275649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2285648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2295898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2305648Sgblack@eecs.umich.edu return latency; 2315647Sgblack@eecs.umich.edu} 2325691Sgblack@eecs.umich.eduvoid 2335691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2345691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2355691Sgblack@eecs.umich.edu{ 2365691Sgblack@eecs.umich.edu /* 2375691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2385691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2395691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2405691Sgblack@eecs.umich.edu */ 2415691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2425691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2435691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2445691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2455691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2465691Sgblack@eecs.umich.edu if (vector > IRRV) 2475691Sgblack@eecs.umich.edu IRRV = vector; 2485691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2495691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2505691Sgblack@eecs.umich.edu if (level) { 2515691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2525691Sgblack@eecs.umich.edu } else { 2535691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2545691Sgblack@eecs.umich.edu } 2555691Sgblack@eecs.umich.edu } 2565691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2575691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2585691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2595691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2605691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2615691Sgblack@eecs.umich.edu smiVector = vector; 2625691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2635691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2645691Sgblack@eecs.umich.edu nmiVector = vector; 2655691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2665691Sgblack@eecs.umich.edu pendingExtInt = true; 2675691Sgblack@eecs.umich.edu extIntVector = vector; 2685691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2695691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2705691Sgblack@eecs.umich.edu initVector = vector; 2716066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2726066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2736050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2746050Sgblack@eecs.umich.edu startupVector = vector; 2755691Sgblack@eecs.umich.edu } 2765691Sgblack@eecs.umich.edu } 2775811Sgblack@eecs.umich.edu cpu->wakeup(); 2785691Sgblack@eecs.umich.edu} 2795647Sgblack@eecs.umich.edu 2806041Sgblack@eecs.umich.edu 2816041Sgblack@eecs.umich.eduvoid 2826041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2836041Sgblack@eecs.umich.edu{ 2846136Sgblack@eecs.umich.edu assert(newCPU); 2856136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 2866136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 2876136Sgblack@eecs.umich.edu " with different IDs.\n"); 2886136Sgblack@eecs.umich.edu } 2896041Sgblack@eecs.umich.edu cpu = newCPU; 2906136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 2916136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 2926041Sgblack@eecs.umich.edu} 2936041Sgblack@eecs.umich.edu 2946041Sgblack@eecs.umich.edu 2956137Sgblack@eecs.umich.eduvoid 2966137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 2976137Sgblack@eecs.umich.edu{ 2987913SBrad.Beckmann@amd.com // 2997913SBrad.Beckmann@amd.com // The local apic must register its address ranges on both its pio port 3007913SBrad.Beckmann@amd.com // via the basicpiodevice(piodevice) init() function and its int port 3017913SBrad.Beckmann@amd.com // that it inherited from IntDev. Note IntDev is not a SimObject itself. 3027913SBrad.Beckmann@amd.com // 3036137Sgblack@eecs.umich.edu BasicPioDevice::init(); 3047913SBrad.Beckmann@amd.com IntDev::init(); 3058742Sgblack@eecs.umich.edu#if FULL_SYSTEM 3066137Sgblack@eecs.umich.edu Pc * pc = dynamic_cast<Pc *>(platform); 3076137Sgblack@eecs.umich.edu assert(pc); 3086137Sgblack@eecs.umich.edu pc->southBridge->ioApic->registerLocalApic(initialApicId, this); 3098742Sgblack@eecs.umich.edu#endif 3106137Sgblack@eecs.umich.edu} 3116137Sgblack@eecs.umich.edu 3126137Sgblack@eecs.umich.edu 3135651Sgblack@eecs.umich.eduTick 3145651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3155651Sgblack@eecs.umich.edu{ 3166136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3175651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3185651Sgblack@eecs.umich.edu switch(offset) 3195651Sgblack@eecs.umich.edu { 3205651Sgblack@eecs.umich.edu case 0: 3215654Sgblack@eecs.umich.edu { 3225654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3235654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3245654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3255697Snate@binkert.org message.vector); 3265655Sgblack@eecs.umich.edu 3275691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3285691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3295654Sgblack@eecs.umich.edu } 3305651Sgblack@eecs.umich.edu break; 3315651Sgblack@eecs.umich.edu default: 3325651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3335651Sgblack@eecs.umich.edu offset); 3345651Sgblack@eecs.umich.edu break; 3355651Sgblack@eecs.umich.edu } 3366064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3375651Sgblack@eecs.umich.edu return latency; 3385651Sgblack@eecs.umich.edu} 3395651Sgblack@eecs.umich.edu 3405651Sgblack@eecs.umich.edu 3416065Sgblack@eecs.umich.eduTick 3426065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3436065Sgblack@eecs.umich.edu{ 3446065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3456065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3466069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3476069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3486069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3496069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3506069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3516069Sgblack@eecs.umich.edu } 3526065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3536065Sgblack@eecs.umich.edu return 0; 3546065Sgblack@eecs.umich.edu} 3556065Sgblack@eecs.umich.edu 3566065Sgblack@eecs.umich.edu 3576041Sgblack@eecs.umich.eduvoid 3586041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3596041Sgblack@eecs.umich.edu{ 3606041Sgblack@eecs.umich.edu range_list.clear(); 3616136Sgblack@eecs.umich.edu Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3626136Sgblack@eecs.umich.edu x86LocalAPICAddress(initialApicId, 0) + 3636136Sgblack@eecs.umich.edu PageBytes); 3646061Sgblack@eecs.umich.edu range_list.push_back(range); 3656061Sgblack@eecs.umich.edu pioAddr = range.start; 3666041Sgblack@eecs.umich.edu} 3676041Sgblack@eecs.umich.edu 3686041Sgblack@eecs.umich.edu 3696041Sgblack@eecs.umich.eduvoid 3706041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3716041Sgblack@eecs.umich.edu{ 3726041Sgblack@eecs.umich.edu range_list.clear(); 3736136Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3746136Sgblack@eecs.umich.edu x86InterruptAddress(initialApicId, 0) + 3756136Sgblack@eecs.umich.edu PhysAddrAPICRangeSize)); 3766041Sgblack@eecs.umich.edu} 3776041Sgblack@eecs.umich.edu 3786041Sgblack@eecs.umich.edu 3795647Sgblack@eecs.umich.eduuint32_t 3805648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3815647Sgblack@eecs.umich.edu{ 3825647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3835647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3845647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3855647Sgblack@eecs.umich.edu } 3865647Sgblack@eecs.umich.edu switch (reg) { 3875647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3885647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3895647Sgblack@eecs.umich.edu break; 3905647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3915647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3925647Sgblack@eecs.umich.edu break; 3935647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3945647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3955647Sgblack@eecs.umich.edu break; 3965647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3975647Sgblack@eecs.umich.edu { 3985848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3995848Sgblack@eecs.umich.edu assert(clock); 4005848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 4015848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 4025848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 4035848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 4047823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 4055848Sgblack@eecs.umich.edu // Turn that into a count. 4065848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 4075848Sgblack@eecs.umich.edu return val; 4085848Sgblack@eecs.umich.edu } else { 4095848Sgblack@eecs.umich.edu return 0; 4105848Sgblack@eecs.umich.edu } 4115647Sgblack@eecs.umich.edu } 4125647Sgblack@eecs.umich.edu default: 4135647Sgblack@eecs.umich.edu break; 4145647Sgblack@eecs.umich.edu } 4155648Sgblack@eecs.umich.edu return regs[reg]; 4165647Sgblack@eecs.umich.edu} 4175647Sgblack@eecs.umich.edu 4185647Sgblack@eecs.umich.eduvoid 4195648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4205647Sgblack@eecs.umich.edu{ 4215647Sgblack@eecs.umich.edu uint32_t newVal = val; 4225647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4235647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4245647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4255647Sgblack@eecs.umich.edu } 4265647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4275647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4285647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4295647Sgblack@eecs.umich.edu } 4305647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4315647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4325647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4335647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4345647Sgblack@eecs.umich.edu } 4355647Sgblack@eecs.umich.edu switch (reg) { 4365647Sgblack@eecs.umich.edu case APIC_ID: 4375647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4385647Sgblack@eecs.umich.edu break; 4395647Sgblack@eecs.umich.edu case APIC_VERSION: 4405647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4415647Sgblack@eecs.umich.edu return; 4425647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4435647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4445647Sgblack@eecs.umich.edu break; 4455647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4465647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4475647Sgblack@eecs.umich.edu break; 4485647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4495647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4505647Sgblack@eecs.umich.edu break; 4515647Sgblack@eecs.umich.edu case APIC_EOI: 4525690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4535690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4545690Sgblack@eecs.umich.edu updateISRV(); 4555690Sgblack@eecs.umich.edu return; 4565647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4575647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4605647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4615647Sgblack@eecs.umich.edu break; 4625647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4635647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4645647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4655647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4665647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4675647Sgblack@eecs.umich.edu break; 4685647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4695647Sgblack@eecs.umich.edu { 4705647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4715647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4725647Sgblack@eecs.umich.edu newVal = 0; 4735647Sgblack@eecs.umich.edu } else { 4745647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4755647Sgblack@eecs.umich.edu return; 4765647Sgblack@eecs.umich.edu } 4775647Sgblack@eecs.umich.edu 4785647Sgblack@eecs.umich.edu } 4795647Sgblack@eecs.umich.edu break; 4805647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4816046Sgblack@eecs.umich.edu { 4826046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4836046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4846046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4856046Sgblack@eecs.umich.edu newVal = low; 4866046Sgblack@eecs.umich.edu break; 4876046Sgblack@eecs.umich.edu } 4886046Sgblack@eecs.umich.edu low = val; 4896046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4906046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 4916046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 4926712Snate@binkert.org TriggerIntMessage message = 0; 4936046Sgblack@eecs.umich.edu message.destination = high.destination; 4946046Sgblack@eecs.umich.edu message.vector = low.vector; 4956046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4966046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4976046Sgblack@eecs.umich.edu message.level = low.level; 4986046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4996046Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 5006065Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 5016065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 5026138Sgblack@eecs.umich.edu ApicList apics; 5036138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 5046046Sgblack@eecs.umich.edu switch (low.destShorthand) { 5056046Sgblack@eecs.umich.edu case 0: 5066138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 5076138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 5086138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 5096138Sgblack@eecs.umich.edu } 5106138Sgblack@eecs.umich.edu if (message.destMode == 1) { 5116138Sgblack@eecs.umich.edu int dest = message.destination; 5126138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 5136138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5146138Sgblack@eecs.umich.edu if (dest & 0x1) 5156138Sgblack@eecs.umich.edu apics.push_back(i); 5166138Sgblack@eecs.umich.edu dest = dest >> 1; 5176138Sgblack@eecs.umich.edu } 5186138Sgblack@eecs.umich.edu } else { 5196138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5206138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5216138Sgblack@eecs.umich.edu if (i == initialApicId) { 5226138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5236138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5246138Sgblack@eecs.umich.edu } else { 5256138Sgblack@eecs.umich.edu apics.push_back(i); 5266138Sgblack@eecs.umich.edu } 5276138Sgblack@eecs.umich.edu } 5286138Sgblack@eecs.umich.edu } else { 5296138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5306138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5316138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5326138Sgblack@eecs.umich.edu } else { 5336138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5346138Sgblack@eecs.umich.edu } 5356138Sgblack@eecs.umich.edu } 5366138Sgblack@eecs.umich.edu } 5376046Sgblack@eecs.umich.edu break; 5386046Sgblack@eecs.umich.edu case 1: 5396069Sgblack@eecs.umich.edu newVal = val; 5406069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5416069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5426046Sgblack@eecs.umich.edu break; 5436046Sgblack@eecs.umich.edu case 2: 5446069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5456069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5466069Sgblack@eecs.umich.edu // Fall through 5476046Sgblack@eecs.umich.edu case 3: 5486069Sgblack@eecs.umich.edu { 5496069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5506138Sgblack@eecs.umich.edu if (i != initialApicId) { 5516138Sgblack@eecs.umich.edu apics.push_back(i); 5526069Sgblack@eecs.umich.edu } 5536069Sgblack@eecs.umich.edu } 5546069Sgblack@eecs.umich.edu } 5556046Sgblack@eecs.umich.edu break; 5566046Sgblack@eecs.umich.edu } 5576138Sgblack@eecs.umich.edu pendingIPIs += apics.size(); 5586138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, timing); 5596138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5606046Sgblack@eecs.umich.edu } 5615647Sgblack@eecs.umich.edu break; 5625647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5635647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5645647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5655647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5665647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5675647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5685647Sgblack@eecs.umich.edu { 5695647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5705647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5715647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5725647Sgblack@eecs.umich.edu } 5735647Sgblack@eecs.umich.edu break; 5745647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5755648Sgblack@eecs.umich.edu { 5765648Sgblack@eecs.umich.edu assert(clock); 5775648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5785848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5795848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5805848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5815648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5827823Ssteve.reinhardt@amd.com Tick offset = curTick() % clock; 5835648Sgblack@eecs.umich.edu if (offset) { 5845648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5857823Ssteve.reinhardt@amd.com curTick() + (newCount + 1) * clock - offset, true); 5865648Sgblack@eecs.umich.edu } else { 5875648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5887823Ssteve.reinhardt@amd.com curTick() + newCount * clock, true); 5895648Sgblack@eecs.umich.edu } 5905648Sgblack@eecs.umich.edu } 5915647Sgblack@eecs.umich.edu break; 5925647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5935647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5945647Sgblack@eecs.umich.edu return; 5955647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5965647Sgblack@eecs.umich.edu newVal = val & 0xB; 5975647Sgblack@eecs.umich.edu break; 5985647Sgblack@eecs.umich.edu default: 5995647Sgblack@eecs.umich.edu break; 6005647Sgblack@eecs.umich.edu } 6015648Sgblack@eecs.umich.edu regs[reg] = newVal; 6025647Sgblack@eecs.umich.edu return; 6035647Sgblack@eecs.umich.edu} 6045647Sgblack@eecs.umich.edu 6056041Sgblack@eecs.umich.edu 6066041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 6077900Shestness@cs.utexas.edu BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 6087900Shestness@cs.utexas.edu clock(0), 6096041Sgblack@eecs.umich.edu apicTimerEvent(this), 6106041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 6116041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 6126041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 6136041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 6146050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 6156069Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 6166136Sgblack@eecs.umich.edu pendingIPIs(0), cpu(NULL) 6178742Sgblack@eecs.umich.edu#if FULL_SYSTEM 6188742Sgblack@eecs.umich.edu , platform(p->platform) 6198742Sgblack@eecs.umich.edu#endif 6206041Sgblack@eecs.umich.edu{ 6216041Sgblack@eecs.umich.edu pioSize = PageBytes; 6226041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6236041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6246041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6256041Sgblack@eecs.umich.edu ISRV = 0; 6266041Sgblack@eecs.umich.edu IRRV = 0; 6276041Sgblack@eecs.umich.edu} 6286041Sgblack@eecs.umich.edu 6296041Sgblack@eecs.umich.edu 6305654Sgblack@eecs.umich.edubool 6315704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6325654Sgblack@eecs.umich.edu{ 6335654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6345689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6355689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6365654Sgblack@eecs.umich.edu return true; 6375689Sgblack@eecs.umich.edu } 6385655Sgblack@eecs.umich.edu if (rflags.intf) { 6395689Sgblack@eecs.umich.edu if (pendingExtInt) { 6405689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6415655Sgblack@eecs.umich.edu return true; 6425689Sgblack@eecs.umich.edu } 6435655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6445689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6455689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6465655Sgblack@eecs.umich.edu return true; 6475689Sgblack@eecs.umich.edu } 6485654Sgblack@eecs.umich.edu } 6495654Sgblack@eecs.umich.edu return false; 6505654Sgblack@eecs.umich.edu} 6515654Sgblack@eecs.umich.edu 6525654Sgblack@eecs.umich.eduFault 6535704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6545654Sgblack@eecs.umich.edu{ 6555704Snate@binkert.org assert(checkInterrupts(tc)); 6565655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6575655Sgblack@eecs.umich.edu // check for. 6585655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6595655Sgblack@eecs.umich.edu if (pendingSmi) { 6605689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6615655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6625655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6635689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6645691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6655655Sgblack@eecs.umich.edu } else if (pendingInit) { 6665689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6675691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6686050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6696050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6706050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6715655Sgblack@eecs.umich.edu } else { 6725655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6735655Sgblack@eecs.umich.edu "ints were pending.\n"); 6745655Sgblack@eecs.umich.edu return NoFault; 6755655Sgblack@eecs.umich.edu } 6765655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6775689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6785691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6795655Sgblack@eecs.umich.edu } else { 6805689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6815655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6825655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6835655Sgblack@eecs.umich.edu } 6845654Sgblack@eecs.umich.edu} 6855654Sgblack@eecs.umich.edu 6865654Sgblack@eecs.umich.eduvoid 6875704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6885654Sgblack@eecs.umich.edu{ 6895704Snate@binkert.org assert(checkInterrupts(tc)); 6905655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6915655Sgblack@eecs.umich.edu if (pendingSmi) { 6925689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6935655Sgblack@eecs.umich.edu pendingSmi = false; 6945655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6955689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6965655Sgblack@eecs.umich.edu pendingNmi = false; 6975655Sgblack@eecs.umich.edu } else if (pendingInit) { 6985689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6995655Sgblack@eecs.umich.edu pendingInit = false; 7006066Sgblack@eecs.umich.edu startedUp = false; 7016050Sgblack@eecs.umich.edu } else if (pendingStartup) { 7026050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 7036050Sgblack@eecs.umich.edu pendingStartup = false; 7046066Sgblack@eecs.umich.edu startedUp = true; 7055655Sgblack@eecs.umich.edu } 7066050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 7075655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 7085655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 7095655Sgblack@eecs.umich.edu pendingExtInt = false; 7105655Sgblack@eecs.umich.edu } else { 7115689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7125655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7135655Sgblack@eecs.umich.edu ISRV = IRRV; 7145655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7155655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7165655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7175655Sgblack@eecs.umich.edu updateIRRV(); 7185655Sgblack@eecs.umich.edu } 7195654Sgblack@eecs.umich.edu} 7205654Sgblack@eecs.umich.edu 7217902Shestness@cs.utexas.eduvoid 7227902Shestness@cs.utexas.eduX86ISA::Interrupts::serialize(std::ostream &os) 7237902Shestness@cs.utexas.edu{ 7247902Shestness@cs.utexas.edu SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7257902Shestness@cs.utexas.edu SERIALIZE_SCALAR(clock); 7267902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingSmi); 7277902Shestness@cs.utexas.edu SERIALIZE_SCALAR(smiVector); 7287902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingNmi); 7297902Shestness@cs.utexas.edu SERIALIZE_SCALAR(nmiVector); 7307902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingExtInt); 7317902Shestness@cs.utexas.edu SERIALIZE_SCALAR(extIntVector); 7327902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingInit); 7337902Shestness@cs.utexas.edu SERIALIZE_SCALAR(initVector); 7347902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingStartup); 7357902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startupVector); 7367902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startedUp); 7377902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingUnmaskableInt); 7387902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingIPIs); 7397902Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRRV); 7407902Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISRV); 7417902Shestness@cs.utexas.edu bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 7427902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventScheduled); 7437902Shestness@cs.utexas.edu Tick apicTimerEventTick = apicTimerEvent.when(); 7447902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventTick); 7457902Shestness@cs.utexas.edu} 7467902Shestness@cs.utexas.edu 7477902Shestness@cs.utexas.eduvoid 7487902Shestness@cs.utexas.eduX86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 7497902Shestness@cs.utexas.edu{ 7507902Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7517902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(clock); 7527902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingSmi); 7537902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(smiVector); 7547902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingNmi); 7557902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(nmiVector); 7567902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingExtInt); 7577902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(extIntVector); 7587902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingInit); 7597902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initVector); 7607902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingStartup); 7617902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startupVector); 7627902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startedUp); 7637902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingUnmaskableInt); 7647902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingIPIs); 7657902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRRV); 7667902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISRV); 7677902Shestness@cs.utexas.edu bool apicTimerEventScheduled; 7687902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventScheduled); 7697902Shestness@cs.utexas.edu if (apicTimerEventScheduled) { 7707902Shestness@cs.utexas.edu Tick apicTimerEventTick; 7717902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventTick); 7727902Shestness@cs.utexas.edu if (apicTimerEvent.scheduled()) { 7737902Shestness@cs.utexas.edu reschedule(apicTimerEvent, apicTimerEventTick, true); 7747902Shestness@cs.utexas.edu } else { 7757902Shestness@cs.utexas.edu schedule(apicTimerEvent, apicTimerEventTick); 7767902Shestness@cs.utexas.edu } 7777902Shestness@cs.utexas.edu } 7787902Shestness@cs.utexas.edu} 7797902Shestness@cs.utexas.edu 7805647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7815647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7825647Sgblack@eecs.umich.edu{ 7835647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7845647Sgblack@eecs.umich.edu} 785