static_inst.hh revision 7720
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Gabe Black 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com#ifndef __ARCH_X86_INSTS_STATICINST_HH__ 4110259SAndrew.Bardsley@arm.com#define __ARCH_X86_INSTS_STATICINST_HH__ 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.com#include "base/trace.hh" 4410259SAndrew.Bardsley@arm.com#include "cpu/static_inst.hh" 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.comnamespace X86ISA 4710259SAndrew.Bardsley@arm.com{ 4810259SAndrew.Bardsley@arm.com /** 4910259SAndrew.Bardsley@arm.com * Class for register indices passed to instruction constructors. Using a 5010259SAndrew.Bardsley@arm.com * wrapper struct for these lets take advantage of the compiler's type 5110259SAndrew.Bardsley@arm.com * checking. 5210259SAndrew.Bardsley@arm.com */ 5310259SAndrew.Bardsley@arm.com struct InstRegIndex 5410259SAndrew.Bardsley@arm.com { 5510259SAndrew.Bardsley@arm.com RegIndex idx; 5610259SAndrew.Bardsley@arm.com explicit InstRegIndex(RegIndex _idx) : idx(_idx) 5710259SAndrew.Bardsley@arm.com {} 5810259SAndrew.Bardsley@arm.com }; 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com /** 6110259SAndrew.Bardsley@arm.com * Base class for all X86 static instructions. 6210259SAndrew.Bardsley@arm.com */ 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.com class X86StaticInst : public StaticInst 6510259SAndrew.Bardsley@arm.com { 6610259SAndrew.Bardsley@arm.com protected: 6710259SAndrew.Bardsley@arm.com // Constructor. 6810259SAndrew.Bardsley@arm.com X86StaticInst(const char *mnem, 6910259SAndrew.Bardsley@arm.com ExtMachInst _machInst, OpClass __opClass) 7010259SAndrew.Bardsley@arm.com : StaticInst(mnem, _machInst, __opClass) 7110259SAndrew.Bardsley@arm.com { 7210259SAndrew.Bardsley@arm.com } 7310259SAndrew.Bardsley@arm.com 7410259SAndrew.Bardsley@arm.com std::string generateDisassembly(Addr pc, 7510259SAndrew.Bardsley@arm.com const SymbolTable *symtab) const; 7610259SAndrew.Bardsley@arm.com 7710259SAndrew.Bardsley@arm.com void printMnemonic(std::ostream &os, const char * mnemonic) const; 7810259SAndrew.Bardsley@arm.com void printMnemonic(std::ostream &os, const char * instMnemonic, 7910259SAndrew.Bardsley@arm.com const char * mnemonic) const; 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.com void printSegment(std::ostream &os, int segment) const; 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.com void printReg(std::ostream &os, int reg, int size) const; 8410259SAndrew.Bardsley@arm.com void printSrcReg(std::ostream &os, int reg, int size) const; 8510259SAndrew.Bardsley@arm.com void printDestReg(std::ostream &os, int reg, int size) const; 8610259SAndrew.Bardsley@arm.com void printMem(std::ostream &os, uint8_t segment, 8710259SAndrew.Bardsley@arm.com uint8_t scale, RegIndex index, RegIndex base, 8810259SAndrew.Bardsley@arm.com uint64_t disp, uint8_t addressSize, bool rip) const; 8910259SAndrew.Bardsley@arm.com 9010259SAndrew.Bardsley@arm.com inline uint64_t merge(uint64_t into, uint64_t val, int size) const 9110259SAndrew.Bardsley@arm.com { 9210259SAndrew.Bardsley@arm.com X86IntReg reg = into; 9310259SAndrew.Bardsley@arm.com if(_destRegIdx[0] & IntFoldBit) 9410259SAndrew.Bardsley@arm.com { 9510259SAndrew.Bardsley@arm.com reg.H = val; 9610259SAndrew.Bardsley@arm.com return reg; 9710259SAndrew.Bardsley@arm.com } 9810259SAndrew.Bardsley@arm.com switch(size) 9910259SAndrew.Bardsley@arm.com { 10010259SAndrew.Bardsley@arm.com case 1: 10110259SAndrew.Bardsley@arm.com reg.L = val; 10210259SAndrew.Bardsley@arm.com break; 10310259SAndrew.Bardsley@arm.com case 2: 10410259SAndrew.Bardsley@arm.com reg.X = val; 10510259SAndrew.Bardsley@arm.com break; 10610259SAndrew.Bardsley@arm.com case 4: 10710259SAndrew.Bardsley@arm.com //XXX Check if this should be zeroed or sign extended 10810259SAndrew.Bardsley@arm.com reg = 0; 10910259SAndrew.Bardsley@arm.com reg.E = val; 11010259SAndrew.Bardsley@arm.com break; 11110259SAndrew.Bardsley@arm.com case 8: 11210259SAndrew.Bardsley@arm.com reg.R = val; 11310259SAndrew.Bardsley@arm.com break; 11410259SAndrew.Bardsley@arm.com default: 11510259SAndrew.Bardsley@arm.com panic("Tried to merge with unrecognized size %d.\n", size); 11610259SAndrew.Bardsley@arm.com } 11710259SAndrew.Bardsley@arm.com return reg; 11810259SAndrew.Bardsley@arm.com } 11910259SAndrew.Bardsley@arm.com 12010259SAndrew.Bardsley@arm.com inline uint64_t pick(uint64_t from, int idx, int size) const 12110259SAndrew.Bardsley@arm.com { 12210259SAndrew.Bardsley@arm.com X86IntReg reg = from; 12310259SAndrew.Bardsley@arm.com DPRINTF(X86, "Picking with size %d\n", size); 12410259SAndrew.Bardsley@arm.com if(_srcRegIdx[idx] & IntFoldBit) 12510259SAndrew.Bardsley@arm.com return reg.H; 12610259SAndrew.Bardsley@arm.com switch(size) 12710259SAndrew.Bardsley@arm.com { 12810259SAndrew.Bardsley@arm.com case 1: 12910259SAndrew.Bardsley@arm.com return reg.L; 13010259SAndrew.Bardsley@arm.com case 2: 13110259SAndrew.Bardsley@arm.com return reg.X; 13210259SAndrew.Bardsley@arm.com case 4: 13310259SAndrew.Bardsley@arm.com return reg.E; 13410259SAndrew.Bardsley@arm.com case 8: 13510259SAndrew.Bardsley@arm.com return reg.R; 13610259SAndrew.Bardsley@arm.com default: 13710259SAndrew.Bardsley@arm.com panic("Tried to pick with unrecognized size %d.\n", size); 13810259SAndrew.Bardsley@arm.com } 13910259SAndrew.Bardsley@arm.com } 14010259SAndrew.Bardsley@arm.com 14110259SAndrew.Bardsley@arm.com inline int64_t signedPick(uint64_t from, int idx, int size) const 14210259SAndrew.Bardsley@arm.com { 14310259SAndrew.Bardsley@arm.com X86IntReg reg = from; 14410259SAndrew.Bardsley@arm.com DPRINTF(X86, "Picking with size %d\n", size); 14510259SAndrew.Bardsley@arm.com if(_srcRegIdx[idx] & IntFoldBit) 14610259SAndrew.Bardsley@arm.com return reg.SH; 14710259SAndrew.Bardsley@arm.com switch(size) 14810259SAndrew.Bardsley@arm.com { 14910259SAndrew.Bardsley@arm.com case 1: 15010259SAndrew.Bardsley@arm.com return reg.SL; 15110259SAndrew.Bardsley@arm.com case 2: 15210259SAndrew.Bardsley@arm.com return reg.SX; 15310814Sandreas.hansson@arm.com case 4: 15410259SAndrew.Bardsley@arm.com return reg.SE; 15510259SAndrew.Bardsley@arm.com case 8: 15610259SAndrew.Bardsley@arm.com return reg.SR; 15710259SAndrew.Bardsley@arm.com default: 15810259SAndrew.Bardsley@arm.com panic("Tried to pick with unrecognized size %d.\n", size); 15910259SAndrew.Bardsley@arm.com } 16010259SAndrew.Bardsley@arm.com } 16110259SAndrew.Bardsley@arm.com 16210259SAndrew.Bardsley@arm.com void 16310259SAndrew.Bardsley@arm.com advancePC(PCState &pcState) const 16410259SAndrew.Bardsley@arm.com { 16510259SAndrew.Bardsley@arm.com pcState.advance(); 16610259SAndrew.Bardsley@arm.com } 16710259SAndrew.Bardsley@arm.com }; 16810259SAndrew.Bardsley@arm.com} 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.com#endif //__ARCH_X86_INSTS_STATICINST_HH__ 17110259SAndrew.Bardsley@arm.com