static_inst.hh revision 7087
12623SN/A/* 210596Sgabeblack@google.com * Copyright (c) 2007 The Hewlett-Packard Development Company 311147Smitch.hayenga@arm.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67725SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77725SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87725SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97725SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107725SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117725SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127725SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137725SAli.Saidi@ARM.com * 147725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 152623SN/A * modification, are permitted provided that the following conditions are 162623SN/A * met: redistributions of source code must retain the above copyright 172623SN/A * notice, this list of conditions and the following disclaimer; 182623SN/A * redistributions in binary form must reproduce the above copyright 192623SN/A * notice, this list of conditions and the following disclaimer in the 202623SN/A * documentation and/or other materials provided with the distribution; 212623SN/A * neither the name of the copyright holders nor the names of its 222623SN/A * contributors may be used to endorse or promote products derived from 232623SN/A * this software without specific prior written permission. 242623SN/A * 252623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362623SN/A * 372623SN/A * Authors: Gabe Black 382623SN/A */ 392623SN/A 402665Ssaidi@eecs.umich.edu#ifndef __ARCH_X86_INSTS_STATICINST_HH__ 412665Ssaidi@eecs.umich.edu#define __ARCH_X86_INSTS_STATICINST_HH__ 422623SN/A 432623SN/A#include "base/trace.hh" 443170Sstever@eecs.umich.edu#include "cpu/static_inst.hh" 458105Sgblack@eecs.umich.edu 462623SN/Anamespace X86ISA 474040Ssaidi@eecs.umich.edu{ 486658Snate@binkert.org /** 498229Snate@binkert.org * Class for register indices passed to instruction constructors. Using a 502623SN/A * wrapper struct for these lets take advantage of the compiler's type 518232Snate@binkert.org * checking. 529152Satgutier@umich.edu */ 538232Snate@binkert.org struct InstRegIndex 548232Snate@binkert.org { 553348Sbinkertn@umich.edu RegIndex idx; 563348Sbinkertn@umich.edu explicit InstRegIndex(RegIndex _idx) : idx(_idx) 574762Snate@binkert.org {} 587678Sgblack@eecs.umich.edu }; 598779Sgblack@eecs.umich.edu 602901Ssaidi@eecs.umich.edu /** 612623SN/A * Base class for all X86 static instructions. 6210529Smorr@cs.wisc.edu */ 6310529Smorr@cs.wisc.edu 642623SN/A class X86StaticInst : public StaticInst 652623SN/A { 662623SN/A protected: 672623SN/A // Constructor. 682623SN/A X86StaticInst(const char *mnem, 692623SN/A ExtMachInst _machInst, OpClass __opClass) 7011147Smitch.hayenga@arm.com : StaticInst(mnem, _machInst, __opClass) 712623SN/A { 722623SN/A } 732623SN/A 748707Sandreas.hansson@arm.com std::string generateDisassembly(Addr pc, 752948Ssaidi@eecs.umich.edu const SymbolTable *symtab) const; 762948Ssaidi@eecs.umich.edu 775606Snate@binkert.org void printMnemonic(std::ostream &os, const char * mnemonic) const; 782948Ssaidi@eecs.umich.edu void printMnemonic(std::ostream &os, const char * instMnemonic, 792948Ssaidi@eecs.umich.edu const char * mnemonic) const; 805529Snate@binkert.org 818707Sandreas.hansson@arm.com void printSegment(std::ostream &os, int segment) const; 829179Sandreas.hansson@arm.com 8310913Sandreas.sandberg@arm.com void printReg(std::ostream &os, int reg, int size) const; 842623SN/A void printSrcReg(std::ostream &os, int reg, int size) const; 852623SN/A void printDestReg(std::ostream &os, int reg, int size) const; 862623SN/A void printMem(std::ostream &os, uint8_t segment, 872623SN/A uint8_t scale, RegIndex index, RegIndex base, 882623SN/A uint64_t disp, uint8_t addressSize, bool rip) const; 8910030SAli.Saidi@ARM.com 902623SN/A inline uint64_t merge(uint64_t into, uint64_t val, int size) const 912623SN/A { 922623SN/A X86IntReg reg = into; 932623SN/A if(_destRegIdx[0] & IntFoldBit) 9410913Sandreas.sandberg@arm.com { 9510913Sandreas.sandberg@arm.com reg.H = val; 962798Sktlim@umich.edu return reg; 979448SAndreas.Sandberg@ARM.com } 9810913Sandreas.sandberg@arm.com switch(size) 999448SAndreas.Sandberg@ARM.com { 1009342SAndreas.Sandberg@arm.com case 1: 1019448SAndreas.Sandberg@ARM.com reg.L = val; 1029442SAndreas.Sandberg@ARM.com break; 10311147Smitch.hayenga@arm.com case 2: 10410913Sandreas.sandberg@arm.com reg.X = val; 1052798Sktlim@umich.edu break; 10611147Smitch.hayenga@arm.com case 4: 1079442SAndreas.Sandberg@ARM.com //XXX Check if this should be zeroed or sign extended 1089442SAndreas.Sandberg@ARM.com reg = 0; 1099442SAndreas.Sandberg@ARM.com reg.E = val; 1109442SAndreas.Sandberg@ARM.com break; 1119448SAndreas.Sandberg@ARM.com case 8: 1129648Sdam.sunwoo@arm.com reg.R = val; 1139442SAndreas.Sandberg@ARM.com break; 11410913Sandreas.sandberg@arm.com default: 1152798Sktlim@umich.edu panic("Tried to merge with unrecognized size %d.\n", size); 1162623SN/A } 1172623SN/A return reg; 1182623SN/A } 1199342SAndreas.Sandberg@arm.com 1202623SN/A inline uint64_t pick(uint64_t from, int idx, int size) const 1219442SAndreas.Sandberg@ARM.com { 1229448SAndreas.Sandberg@ARM.com X86IntReg reg = from; 1239448SAndreas.Sandberg@ARM.com DPRINTF(X86, "Picking with size %d\n", size); 1249442SAndreas.Sandberg@ARM.com if(_srcRegIdx[idx] & IntFoldBit) 1255221Ssaidi@eecs.umich.edu return reg.H; 1269523SAndreas.Sandberg@ARM.com switch(size) 1273201Shsul@eecs.umich.edu { 1289448SAndreas.Sandberg@ARM.com case 1: 1299448SAndreas.Sandberg@ARM.com return reg.L; 13011147Smitch.hayenga@arm.com case 2: 13111147Smitch.hayenga@arm.com return reg.X; 13211147Smitch.hayenga@arm.com case 4: 13311147Smitch.hayenga@arm.com return reg.E; 13411147Smitch.hayenga@arm.com case 8: 13511147Smitch.hayenga@arm.com return reg.R; 13611147Smitch.hayenga@arm.com default: 13711147Smitch.hayenga@arm.com panic("Tried to pick with unrecognized size %d.\n", size); 13811147Smitch.hayenga@arm.com } 13911147Smitch.hayenga@arm.com } 14011147Smitch.hayenga@arm.com 14111147Smitch.hayenga@arm.com inline int64_t signedPick(uint64_t from, int idx, int size) const 14211147Smitch.hayenga@arm.com { 14311147Smitch.hayenga@arm.com X86IntReg reg = from; 14411147Smitch.hayenga@arm.com DPRINTF(X86, "Picking with size %d\n", size); 14511147Smitch.hayenga@arm.com if(_srcRegIdx[idx] & IntFoldBit) 14611147Smitch.hayenga@arm.com return reg.SH; 1472623SN/A switch(size) 14811147Smitch.hayenga@arm.com { 14911147Smitch.hayenga@arm.com case 1: 1509442SAndreas.Sandberg@ARM.com return reg.SL; 1512798Sktlim@umich.edu case 2: 1529442SAndreas.Sandberg@ARM.com return reg.SX; 1539442SAndreas.Sandberg@ARM.com case 4: 1549442SAndreas.Sandberg@ARM.com return reg.SE; 15510913Sandreas.sandberg@arm.com case 8: 1569442SAndreas.Sandberg@ARM.com return reg.SR; 1579442SAndreas.Sandberg@ARM.com default: 15811147Smitch.hayenga@arm.com panic("Tried to pick with unrecognized size %d.\n", size); 1599442SAndreas.Sandberg@ARM.com } 1609442SAndreas.Sandberg@ARM.com } 1619442SAndreas.Sandberg@ARM.com }; 1629442SAndreas.Sandberg@ARM.com} 16310913Sandreas.sandberg@arm.com 1649442SAndreas.Sandberg@ARM.com#endif //__ARCH_X86_INSTS_STATICINST_HH__ 1659442SAndreas.Sandberg@ARM.com