microregop.hh revision 4713:c208cec7b5b3 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
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5 * Redistribution and use of this software in source and binary forms,
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40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INSTS_MICROREGOP_HH__
59#define __ARCH_X86_INSTS_MICROREGOP_HH__
60
61#include "arch/x86/insts/microop.hh"
62
63namespace X86ISA
64{
65    namespace ConditionTests
66    {
67        enum CondTest {
68            True,
69            NotFalse = True,
70            ECF,
71            EZF,
72            SZnZF,
73            MSTRZ,
74            STRZ,
75            MSTRC,
76            STRZnZF,
77            OF,
78            CF,
79            ZF,
80            CvZF,
81            SF,
82            PF,
83            SxOF,
84            SxOvZF,
85
86            False,
87            NotTrue = False,
88            NotECF,
89            NotEZF,
90            NotSZnZF,
91            NotMSTRZ,
92            NotSTRZ,
93            NotMSTRC,
94            NotSTRZnZF,
95            NotOF,
96            NotCF,
97            NotZF,
98            NotCvZF,
99            NotSF,
100            NotPF,
101            NotSxOF,
102            NotSxOvZF
103        };
104    }
105
106    /**
107     * Base classes for RegOps which provides a generateDisassembly method.
108     */
109    class RegOpBase : public X86MicroopBase
110    {
111      protected:
112        const RegIndex src1;
113        const RegIndex dest;
114        const uint8_t dataSize;
115        const uint16_t ext;
116
117        // Constructor
118        RegOpBase(ExtMachInst _machInst,
119                const char *mnem, const char *_instMnem,
120                bool isMicro, bool isDelayed,
121                bool isFirst, bool isLast,
122                RegIndex _src1, RegIndex _dest,
123                uint8_t _dataSize, uint16_t _ext,
124                OpClass __opClass) :
125            X86MicroopBase(_machInst, mnem, _instMnem,
126                    isMicro, isDelayed, isFirst, isLast,
127                    __opClass),
128            src1(_src1), dest(_dest),
129            dataSize(_dataSize), ext(_ext)
130        {
131        }
132
133        //Figure out what the condition code flags should be.
134        uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
135                uint64_t _dest, uint64_t _src1, uint64_t _src2,
136                bool subtract = false) const;
137        bool checkCondition(uint64_t flags) const;
138    };
139
140    class RegOp : public RegOpBase
141    {
142      protected:
143        const RegIndex src2;
144
145        // Constructor
146        RegOp(ExtMachInst _machInst,
147                const char *mnem, const char *_instMnem,
148                bool isMicro, bool isDelayed,
149                bool isFirst, bool isLast,
150                RegIndex _src1, RegIndex _src2, RegIndex _dest,
151                uint8_t _dataSize, uint16_t _ext,
152                OpClass __opClass) :
153            RegOpBase(_machInst, mnem, _instMnem,
154                    isMicro, isDelayed, isFirst, isLast,
155                    _src1, _dest, _dataSize, _ext,
156                    __opClass),
157            src2(_src2)
158        {
159        }
160
161        std::string generateDisassembly(Addr pc,
162            const SymbolTable *symtab) const;
163    };
164
165    class RegOpImm : public RegOpBase
166    {
167      protected:
168        const uint8_t imm8;
169
170        // Constructor
171        RegOpImm(ExtMachInst _machInst,
172                const char * mnem, const char *_instMnem,
173                bool isMicro, bool isDelayed,
174                bool isFirst, bool isLast,
175                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
176                uint8_t _dataSize, uint16_t _ext,
177                OpClass __opClass) :
178            RegOpBase(_machInst, mnem, _instMnem,
179                    isMicro, isDelayed, isFirst, isLast,
180                    _src1, _dest, _dataSize, _ext,
181                    __opClass),
182            imm8(_imm8)
183        {
184        }
185
186        std::string generateDisassembly(Addr pc,
187            const SymbolTable *symtab) const;
188    };
189}
190
191#endif //__ARCH_X86_INSTS_MICROREGOP_HH__
192