faults.hh revision 8591:8f23aeaf6a91
16973Stjones1@inf.ed.ac.uk/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 146973Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 156973Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 166973Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 176973Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 186973Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 196973Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 206973Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 216973Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 226973Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 236973Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 246973Stjones1@inf.ed.ac.uk * 256973Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266973Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276973Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286973Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296973Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306973Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316973Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326973Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336973Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346973Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356973Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366973Stjones1@inf.ed.ac.uk * 376973Stjones1@inf.ed.ac.uk * Authors: Gabe Black 386973Stjones1@inf.ed.ac.uk */ 396973Stjones1@inf.ed.ac.uk 406973Stjones1@inf.ed.ac.uk#ifndef __ARCH_X86_FAULTS_HH__ 416973Stjones1@inf.ed.ac.uk#define __ARCH_X86_FAULTS_HH__ 426973Stjones1@inf.ed.ac.uk 436973Stjones1@inf.ed.ac.uk#include <string> 446973Stjones1@inf.ed.ac.uk 456973Stjones1@inf.ed.ac.uk#include "base/bitunion.hh" 466973Stjones1@inf.ed.ac.uk#include "base/misc.hh" 476973Stjones1@inf.ed.ac.uk#include "sim/faults.hh" 487678Sgblack@eecs.umich.edu#include "sim/tlb.hh" 496973Stjones1@inf.ed.ac.uk 506973Stjones1@inf.ed.ac.uknamespace X86ISA 517049Stjones1@inf.ed.ac.uk{ 527049Stjones1@inf.ed.ac.uk // Base class for all x86 "faults" where faults is in the m5 sense 537049Stjones1@inf.ed.ac.uk class X86FaultBase : public FaultBase 547049Stjones1@inf.ed.ac.uk { 557049Stjones1@inf.ed.ac.uk protected: 567049Stjones1@inf.ed.ac.uk const char * faultName; 577049Stjones1@inf.ed.ac.uk const char * mnem; 587049Stjones1@inf.ed.ac.uk uint8_t vector; 597049Stjones1@inf.ed.ac.uk uint64_t errorCode; 607049Stjones1@inf.ed.ac.uk 616973Stjones1@inf.ed.ac.uk X86FaultBase(const char * _faultName, const char * _mnem, 626973Stjones1@inf.ed.ac.uk const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1) 636973Stjones1@inf.ed.ac.uk : faultName(_faultName), mnem(_mnem), 646973Stjones1@inf.ed.ac.uk vector(_vector), errorCode(_errorCode) 656973Stjones1@inf.ed.ac.uk { 666973Stjones1@inf.ed.ac.uk } 676973Stjones1@inf.ed.ac.uk 687944SGiacomo.Gabrielli@arm.com const char * name() const 696973Stjones1@inf.ed.ac.uk { 706973Stjones1@inf.ed.ac.uk return faultName; 716973Stjones1@inf.ed.ac.uk } 726973Stjones1@inf.ed.ac.uk 736973Stjones1@inf.ed.ac.uk virtual bool isBenign() 746973Stjones1@inf.ed.ac.uk { 756973Stjones1@inf.ed.ac.uk return true; 766973Stjones1@inf.ed.ac.uk } 777049Stjones1@inf.ed.ac.uk 787049Stjones1@inf.ed.ac.uk virtual const char * mnemonic() const 797049Stjones1@inf.ed.ac.uk { 807049Stjones1@inf.ed.ac.uk return mnem; 816973Stjones1@inf.ed.ac.uk } 826973Stjones1@inf.ed.ac.uk 837944SGiacomo.Gabrielli@arm.com virtual bool isSoft() 847944SGiacomo.Gabrielli@arm.com { 856973Stjones1@inf.ed.ac.uk return false; 866973Stjones1@inf.ed.ac.uk } 876973Stjones1@inf.ed.ac.uk 886973Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 896973Stjones1@inf.ed.ac.uk void invoke(ThreadContext * tc, 907049Stjones1@inf.ed.ac.uk StaticInstPtr inst = StaticInst::nullStaticInstPtr); 917049Stjones1@inf.ed.ac.uk 927049Stjones1@inf.ed.ac.uk virtual std::string describe() const; 937049Stjones1@inf.ed.ac.uk#endif 947049Stjones1@inf.ed.ac.uk }; 956973Stjones1@inf.ed.ac.uk 966973Stjones1@inf.ed.ac.uk // Base class for x86 faults which behave as if the underlying instruction 976973Stjones1@inf.ed.ac.uk // didn't happen. 987944SGiacomo.Gabrielli@arm.com class X86Fault : public X86FaultBase 997944SGiacomo.Gabrielli@arm.com { 1007944SGiacomo.Gabrielli@arm.com protected: 1016973Stjones1@inf.ed.ac.uk X86Fault(const char * name, const char * mnem, 1026973Stjones1@inf.ed.ac.uk const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 1036973Stjones1@inf.ed.ac.uk : X86FaultBase(name, mnem, vector, _errorCode) 1046973Stjones1@inf.ed.ac.uk {} 1056973Stjones1@inf.ed.ac.uk }; 1067049Stjones1@inf.ed.ac.uk 1077049Stjones1@inf.ed.ac.uk // Base class for x86 traps which behave as if the underlying instruction 1087049Stjones1@inf.ed.ac.uk // completed. 1097049Stjones1@inf.ed.ac.uk class X86Trap : public X86FaultBase 1107049Stjones1@inf.ed.ac.uk { 1117049Stjones1@inf.ed.ac.uk protected: 1127049Stjones1@inf.ed.ac.uk X86Trap(const char * name, const char * mnem, 1136973Stjones1@inf.ed.ac.uk const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 11410379Sandreas.hansson@arm.com : X86FaultBase(name, mnem, vector, _errorCode) 1156973Stjones1@inf.ed.ac.uk {} 1166973Stjones1@inf.ed.ac.uk 1176973Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 1186973Stjones1@inf.ed.ac.uk void invoke(ThreadContext * tc, 1196973Stjones1@inf.ed.ac.uk StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1206973Stjones1@inf.ed.ac.uk#endif 1216973Stjones1@inf.ed.ac.uk }; 1226973Stjones1@inf.ed.ac.uk 1236973Stjones1@inf.ed.ac.uk // Base class for x86 aborts which seem to be catastrophic failures. 1246973Stjones1@inf.ed.ac.uk class X86Abort : public X86FaultBase 1256973Stjones1@inf.ed.ac.uk { 1266973Stjones1@inf.ed.ac.uk protected: 1276973Stjones1@inf.ed.ac.uk X86Abort(const char * name, const char * mnem, 1286973Stjones1@inf.ed.ac.uk const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 1296973Stjones1@inf.ed.ac.uk : X86FaultBase(name, mnem, vector, _errorCode) 1306973Stjones1@inf.ed.ac.uk {} 1317049Stjones1@inf.ed.ac.uk 1327049Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 1337049Stjones1@inf.ed.ac.uk void invoke(ThreadContext * tc, 1347049Stjones1@inf.ed.ac.uk StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1356973Stjones1@inf.ed.ac.uk#endif 1366973Stjones1@inf.ed.ac.uk }; 1376973Stjones1@inf.ed.ac.uk 1386973Stjones1@inf.ed.ac.uk // Base class for x86 interrupts. 1396973Stjones1@inf.ed.ac.uk class X86Interrupt : public X86FaultBase 1406973Stjones1@inf.ed.ac.uk { 1416973Stjones1@inf.ed.ac.uk protected: 1426973Stjones1@inf.ed.ac.uk X86Interrupt(const char * name, const char * mnem, 1436973Stjones1@inf.ed.ac.uk const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1) 1446973Stjones1@inf.ed.ac.uk : X86FaultBase(name, mnem, _vector, _errorCode) 1456973Stjones1@inf.ed.ac.uk {} 1466973Stjones1@inf.ed.ac.uk }; 1476973Stjones1@inf.ed.ac.uk 1487049Stjones1@inf.ed.ac.uk class UnimpInstFault : public FaultBase 1496973Stjones1@inf.ed.ac.uk { 1506973Stjones1@inf.ed.ac.uk public: 1516973Stjones1@inf.ed.ac.uk const char * name() const 1526973Stjones1@inf.ed.ac.uk { 1536973Stjones1@inf.ed.ac.uk return "unimplemented_micro"; 1546973Stjones1@inf.ed.ac.uk } 1557049Stjones1@inf.ed.ac.uk 1567049Stjones1@inf.ed.ac.uk void invoke(ThreadContext * tc, 1577049Stjones1@inf.ed.ac.uk StaticInstPtr inst = StaticInst::nullStaticInstPtr) 1587049Stjones1@inf.ed.ac.uk { 1597049Stjones1@inf.ed.ac.uk panic("Unimplemented instruction!"); 1606973Stjones1@inf.ed.ac.uk } 1616973Stjones1@inf.ed.ac.uk }; 1626973Stjones1@inf.ed.ac.uk 1636973Stjones1@inf.ed.ac.uk // Below is a summary of the interrupt/exception information in the 1646973Stjones1@inf.ed.ac.uk // architecture manuals. 1656973Stjones1@inf.ed.ac.uk 1667049Stjones1@inf.ed.ac.uk // Class | Type | vector | Cause | mnem 1677049Stjones1@inf.ed.ac.uk //------------------------------------------------------------------------ 1687049Stjones1@inf.ed.ac.uk //Contrib Fault 0 Divide-by-Zero-Error #DE 1697049Stjones1@inf.ed.ac.uk //Benign Either 1 Debug #DB 1707049Stjones1@inf.ed.ac.uk //Benign Interrupt 2 Non-Maskable-Interrupt #NMI 1716973Stjones1@inf.ed.ac.uk //Benign Trap 3 Breakpoint #BP 1726973Stjones1@inf.ed.ac.uk //Benign Trap 4 Overflow #OF 1736973Stjones1@inf.ed.ac.uk //Benign Fault 5 Bound-Range #BR 1746973Stjones1@inf.ed.ac.uk //Benign Fault 6 Invalid-Opcode #UD 1756973Stjones1@inf.ed.ac.uk //Benign Fault 7 Device-Not-Available #NM 1766973Stjones1@inf.ed.ac.uk //Benign Abort 8 Double-Fault #DF 1777049Stjones1@inf.ed.ac.uk // 9 Coprocessor-Segment-Overrun 1786973Stjones1@inf.ed.ac.uk //Contrib Fault 10 Invalid-TSS #TS 1796973Stjones1@inf.ed.ac.uk //Contrib Fault 11 Segment-Not-Present #NP 1806973Stjones1@inf.ed.ac.uk //Contrib Fault 12 Stack #SS 1816973Stjones1@inf.ed.ac.uk //Contrib Fault 13 General-Protection #GP 1826973Stjones1@inf.ed.ac.uk //Either Fault 14 Page-Fault #PF 1836973Stjones1@inf.ed.ac.uk // 15 Reserved 1847049Stjones1@inf.ed.ac.uk //Benign Fault 16 x87 Floating-Point Exception Pending #MF 1857049Stjones1@inf.ed.ac.uk //Benign Fault 17 Alignment-Check #AC 1867049Stjones1@inf.ed.ac.uk //Benign Abort 18 Machine-Check #MC 1877049Stjones1@inf.ed.ac.uk //Benign Fault 19 SIMD Floating-Point #XF 1887049Stjones1@inf.ed.ac.uk // 20-29 Reserved 1896973Stjones1@inf.ed.ac.uk //Contrib ? 30 Security Exception #SX 1906973Stjones1@inf.ed.ac.uk // 31 Reserved 1916973Stjones1@inf.ed.ac.uk //Benign Interrupt 0-255 External Interrupts #INTR 1926973Stjones1@inf.ed.ac.uk //Benign Interrupt 0-255 Software Interrupts INTn 1936973Stjones1@inf.ed.ac.uk 1946973Stjones1@inf.ed.ac.uk class DivideByZero : public X86Fault 1957049Stjones1@inf.ed.ac.uk { 1966973Stjones1@inf.ed.ac.uk public: 1976973Stjones1@inf.ed.ac.uk DivideByZero() : 1986973Stjones1@inf.ed.ac.uk X86Fault("Divide-by-Zero-Error", "#DE", 0) 1996973Stjones1@inf.ed.ac.uk {} 2006973Stjones1@inf.ed.ac.uk }; 2016973Stjones1@inf.ed.ac.uk 2026973Stjones1@inf.ed.ac.uk class DebugException : public X86FaultBase 2036973Stjones1@inf.ed.ac.uk { 2046973Stjones1@inf.ed.ac.uk public: 2056973Stjones1@inf.ed.ac.uk DebugException() : 2066973Stjones1@inf.ed.ac.uk X86FaultBase("Debug", "#DB", 1) 2077049Stjones1@inf.ed.ac.uk {} 2087049Stjones1@inf.ed.ac.uk }; 2097049Stjones1@inf.ed.ac.uk 2107049Stjones1@inf.ed.ac.uk class NonMaskableInterrupt : public X86Interrupt 2117049Stjones1@inf.ed.ac.uk { 2127049Stjones1@inf.ed.ac.uk public: 2137049Stjones1@inf.ed.ac.uk NonMaskableInterrupt(uint8_t _vector) : 2147049Stjones1@inf.ed.ac.uk X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector) 2157049Stjones1@inf.ed.ac.uk {} 2167049Stjones1@inf.ed.ac.uk }; 2178486Sgblack@eecs.umich.edu 2186973Stjones1@inf.ed.ac.uk class Breakpoint : public X86Trap 2196973Stjones1@inf.ed.ac.uk { 2206973Stjones1@inf.ed.ac.uk public: 2218486Sgblack@eecs.umich.edu Breakpoint() : 2226973Stjones1@inf.ed.ac.uk X86Trap("Breakpoint", "#BP", 3) 2236973Stjones1@inf.ed.ac.uk {} 2246973Stjones1@inf.ed.ac.uk }; 2256973Stjones1@inf.ed.ac.uk 2268486Sgblack@eecs.umich.edu class OverflowTrap : public X86Trap 2276973Stjones1@inf.ed.ac.uk { 2286973Stjones1@inf.ed.ac.uk public: 2296973Stjones1@inf.ed.ac.uk OverflowTrap() : 2306973Stjones1@inf.ed.ac.uk X86Trap("Overflow", "#OF", 4) 2318486Sgblack@eecs.umich.edu {} 2326973Stjones1@inf.ed.ac.uk }; 2336973Stjones1@inf.ed.ac.uk 2346973Stjones1@inf.ed.ac.uk class BoundRange : public X86Fault 2356973Stjones1@inf.ed.ac.uk { 2366973Stjones1@inf.ed.ac.uk public: 2377049Stjones1@inf.ed.ac.uk BoundRange() : 2387944SGiacomo.Gabrielli@arm.com X86Fault("Bound-Range", "#BR", 5) 2397944SGiacomo.Gabrielli@arm.com {} 2407944SGiacomo.Gabrielli@arm.com }; 2417944SGiacomo.Gabrielli@arm.com 2427944SGiacomo.Gabrielli@arm.com class InvalidOpcode : public X86Fault 2437944SGiacomo.Gabrielli@arm.com { 2447944SGiacomo.Gabrielli@arm.com public: 2457944SGiacomo.Gabrielli@arm.com InvalidOpcode() : 2467944SGiacomo.Gabrielli@arm.com X86Fault("Invalid-Opcode", "#UD", 6) 2477944SGiacomo.Gabrielli@arm.com {} 2487049Stjones1@inf.ed.ac.uk 2497049Stjones1@inf.ed.ac.uk#if !FULL_SYSTEM 2507049Stjones1@inf.ed.ac.uk void invoke(ThreadContext * tc, 2516973Stjones1@inf.ed.ac.uk StaticInstPtr inst = StaticInst::nullStaticInstPtr); 25210379Sandreas.hansson@arm.com#endif 2536973Stjones1@inf.ed.ac.uk }; 2546973Stjones1@inf.ed.ac.uk 2556973Stjones1@inf.ed.ac.uk class DeviceNotAvailable : public X86Fault 2566973Stjones1@inf.ed.ac.uk { 2576973Stjones1@inf.ed.ac.uk public: 25810177SMitchell.Hayenga@ARM.com DeviceNotAvailable() : 25910177SMitchell.Hayenga@ARM.com X86Fault("Device-Not-Available", "#NM", 7) 26010177SMitchell.Hayenga@ARM.com {} 26110177SMitchell.Hayenga@ARM.com }; 2626973Stjones1@inf.ed.ac.uk 2636973Stjones1@inf.ed.ac.uk class DoubleFault : public X86Abort 2646973Stjones1@inf.ed.ac.uk { 2656973Stjones1@inf.ed.ac.uk public: 2669258SAli.Saidi@ARM.com DoubleFault() : 2679258SAli.Saidi@ARM.com X86Abort("Double-Fault", "#DF", 8, 0) 2689258SAli.Saidi@ARM.com {} 2699258SAli.Saidi@ARM.com }; 2709258SAli.Saidi@ARM.com 2719258SAli.Saidi@ARM.com class InvalidTSS : public X86Fault 2726973Stjones1@inf.ed.ac.uk { 2736973Stjones1@inf.ed.ac.uk public: 2746973Stjones1@inf.ed.ac.uk InvalidTSS(uint32_t _errorCode) : 275 X86Fault("Invalid-TSS", "#TS", 10, _errorCode) 276 {} 277 }; 278 279 class SegmentNotPresent : public X86Fault 280 { 281 public: 282 SegmentNotPresent(uint32_t _errorCode) : 283 X86Fault("Segment-Not-Present", "#NP", 11, _errorCode) 284 {} 285 }; 286 287 class StackFault : public X86Fault 288 { 289 public: 290 StackFault(uint32_t _errorCode) : 291 X86Fault("Stack", "#SS", 12, _errorCode) 292 {} 293 }; 294 295 class GeneralProtection : public X86Fault 296 { 297 public: 298 GeneralProtection(uint32_t _errorCode) : 299 X86Fault("General-Protection", "#GP", 13, _errorCode) 300 {} 301 }; 302 303 class PageFault : public X86Fault 304 { 305 protected: 306 BitUnion32(PageFaultErrorCode) 307 Bitfield<0> present; 308 Bitfield<1> write; 309 Bitfield<2> user; 310 Bitfield<3> reserved; 311 Bitfield<4> fetch; 312 EndBitUnion(PageFaultErrorCode) 313 314 Addr addr; 315 316 public: 317 PageFault(Addr _addr, uint32_t _errorCode) : 318 X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr) 319 {} 320 321 PageFault(Addr _addr, bool present, BaseTLB::Mode mode, 322 bool user, bool reserved) : 323 X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr) 324 { 325 PageFaultErrorCode code = 0; 326 code.present = present; 327 code.write = (mode == BaseTLB::Write); 328 code.user = user; 329 code.reserved = reserved; 330 code.fetch = (mode == BaseTLB::Execute); 331 errorCode = code; 332 } 333 334 void invoke(ThreadContext * tc, 335 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 336 337#if FULL_SYSTEM 338 virtual std::string describe() const; 339#endif 340 }; 341 342 class X87FpExceptionPending : public X86Fault 343 { 344 public: 345 X87FpExceptionPending() : 346 X86Fault("x87 Floating-Point Exception Pending", "#MF", 16) 347 {} 348 }; 349 350 class AlignmentCheck : public X86Fault 351 { 352 public: 353 AlignmentCheck() : 354 X86Fault("Alignment-Check", "#AC", 17, 0) 355 {} 356 }; 357 358 class MachineCheck : public X86Abort 359 { 360 public: 361 MachineCheck() : 362 X86Abort("Machine-Check", "#MC", 18) 363 {} 364 }; 365 366 class SIMDFloatingPointFault : public X86Fault 367 { 368 public: 369 SIMDFloatingPointFault() : 370 X86Fault("SIMD Floating-Point", "#XF", 19) 371 {} 372 }; 373 374 class SecurityException : public X86FaultBase 375 { 376 public: 377 SecurityException() : 378 X86FaultBase("Security Exception", "#SX", 30) 379 {} 380 }; 381 382 class ExternalInterrupt : public X86Interrupt 383 { 384 public: 385 ExternalInterrupt(uint8_t _vector) : 386 X86Interrupt("External Interrupt", "#INTR", _vector) 387 {} 388 }; 389 390 class SystemManagementInterrupt : public X86Interrupt 391 { 392 public: 393 SystemManagementInterrupt() : 394 X86Interrupt("System Management Interrupt", "#SMI", 0) 395 {} 396 }; 397 398 class InitInterrupt : public X86Interrupt 399 { 400 public: 401 InitInterrupt(uint8_t _vector) : 402 X86Interrupt("INIT Interrupt", "#INIT", _vector) 403 {} 404 405 void invoke(ThreadContext * tc, 406 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 407 }; 408 409 class StartupInterrupt : public X86Interrupt 410 { 411 public: 412 StartupInterrupt(uint8_t _vector) : 413 X86Interrupt("Startup Interrupt", "#SIPI", _vector) 414 {} 415 416 void invoke(ThreadContext * tc, 417 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 418 }; 419 420 class SoftwareInterrupt : public X86Interrupt 421 { 422 public: 423 SoftwareInterrupt(uint8_t _vector) : 424 X86Interrupt("Software Interrupt", "#INTR", _vector) 425 {} 426 427 bool isSoft() 428 { 429 return true; 430 } 431 }; 432}; 433 434#endif // __ARCH_X86_FAULTS_HH__ 435