faults.hh revision 5851 
1/*
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35 * output created using the software may be prepared, but only for
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40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_FAULTS_HH__
59#define __ARCH_X86_FAULTS_HH__
60
61#include "base/misc.hh"
62#include "sim/faults.hh"
63
64namespace X86ISA
65{
66    // Base class for all x86 "faults" where faults is in the m5 sense
67    class X86FaultBase : public FaultBase
68    {
69      protected:
70        const char * faultName;
71        const char * mnem;
72        uint8_t vector;
73        uint64_t errorCode;
74
75        X86FaultBase(const char * _faultName, const char * _mnem,
76                const uint8_t _vector, uint64_t _errorCode = 0) :
77            faultName(_faultName), mnem(_mnem),
78            vector(_vector), errorCode(_errorCode)
79        {
80        }
81
82        const char * name() const
83        {
84            return faultName;
85        }
86
87        virtual bool isBenign()
88        {
89            return true;
90        }
91
92        virtual const char * mnemonic() const
93        {
94            return mnem;
95        }
96
97        void
98        invoke(ThreadContext * tc)
99        {
100            panic("Unimplemented fault %s.\n", name());
101        }
102    };
103
104    // Base class for x86 faults which behave as if the underlying instruction
105    // didn't happen.
106    class X86Fault : public X86FaultBase
107    {
108      protected:
109        X86Fault(const char * name, const char * mnem,
110                const uint8_t vector, uint64_t _errorCode = 0) :
111            X86FaultBase(name, mnem, vector, _errorCode)
112        {}
113    };
114
115    // Base class for x86 traps which behave as if the underlying instruction
116    // completed.
117    class X86Trap : public X86FaultBase
118    {
119      protected:
120        X86Trap(const char * name, const char * mnem,
121                const uint8_t vector, uint64_t _errorCode = 0) :
122            X86FaultBase(name, mnem, vector, _errorCode)
123        {}
124
125#if FULL_SYSTEM
126        void invoke(ThreadContext * tc);
127#endif
128    };
129
130    // Base class for x86 aborts which seem to be catastrophic failures.
131    class X86Abort : public X86FaultBase
132    {
133      protected:
134        X86Abort(const char * name, const char * mnem,
135                const uint8_t vector, uint64_t _errorCode = 0) :
136            X86FaultBase(name, mnem, vector, _errorCode)
137        {}
138
139#if FULL_SYSTEM
140        void invoke(ThreadContext * tc);
141#endif
142    };
143
144    // Base class for x86 interrupts.
145    class X86Interrupt : public X86FaultBase
146    {
147      protected:
148        X86Interrupt(const char * name, const char * mnem,
149                const uint8_t _vector, uint64_t _errorCode = 0) :
150            X86FaultBase(name, mnem, _vector, _errorCode)
151        {}
152
153#if FULL_SYSTEM
154        void invoke(ThreadContext * tc);
155#endif
156    };
157
158    class UnimpInstFault : public FaultBase
159    {
160      public:
161        const char * name() const
162        {
163            return "unimplemented_micro";
164        }
165
166        void invoke(ThreadContext * tc)
167        {
168            panic("Unimplemented instruction!");
169        }
170    };
171
172    static inline Fault genMachineCheckFault()
173    {
174        panic("Machine check fault not implemented in x86!\n");
175    }
176
177    // Below is a summary of the interrupt/exception information in the
178    // architecture manuals.
179
180    // Class  |  Type    | vector |               Cause                 | mnem
181    //------------------------------------------------------------------------
182    //Contrib   Fault     0         Divide-by-Zero-Error                  #DE
183    //Benign    Either    1         Debug                                 #DB
184    //Benign    Interrupt 2         Non-Maskable-Interrupt                #NMI
185    //Benign    Trap      3         Breakpoint                            #BP
186    //Benign    Trap      4         Overflow                              #OF
187    //Benign    Fault     5         Bound-Range                           #BR
188    //Benign    Fault     6         Invalid-Opcode                        #UD
189    //Benign    Fault     7         Device-Not-Available                  #NM
190    //Benign    Abort     8         Double-Fault                          #DF
191    //                    9         Coprocessor-Segment-Overrun
192    //Contrib   Fault     10        Invalid-TSS                           #TS
193    //Contrib   Fault     11        Segment-Not-Present                   #NP
194    //Contrib   Fault     12        Stack                                 #SS
195    //Contrib   Fault     13        General-Protection                    #GP
196    //Either    Fault     14        Page-Fault                            #PF
197    //                    15        Reserved
198    //Benign    Fault     16        x87 Floating-Point Exception Pending  #MF
199    //Benign    Fault     17        Alignment-Check                       #AC
200    //Benign    Abort     18        Machine-Check                         #MC
201    //Benign    Fault     19        SIMD Floating-Point                   #XF
202    //                    20-29     Reserved
203    //Contrib   ?         30        Security Exception                    #SX
204    //                    31        Reserved
205    //Benign    Interrupt 0-255     External Interrupts                   #INTR
206    //Benign    Interrupt 0-255     Software Interrupts                   INTn
207
208    class DivideByZero : public X86Fault
209    {
210      public:
211        DivideByZero() :
212            X86Fault("Divide-by-Zero-Error", "#DE", 0)
213        {}
214    };
215
216    class DebugException : public X86FaultBase
217    {
218      public:
219        DebugException() :
220            X86FaultBase("Debug", "#DB", 1)
221        {}
222    };
223
224    class NonMaskableInterrupt : public X86Interrupt
225    {
226      public:
227        NonMaskableInterrupt(uint8_t _vector) :
228            X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
229        {}
230    };
231
232    class Breakpoint : public X86Trap
233    {
234      public:
235        Breakpoint() :
236            X86Trap("Breakpoint", "#BP", 3)
237        {}
238    };
239
240    class OverflowTrap : public X86Trap
241    {
242      public:
243        OverflowTrap() :
244            X86Trap("Overflow", "#OF", 4)
245        {}
246    };
247
248    class BoundRange : public X86Fault
249    {
250      public:
251        BoundRange() :
252            X86Fault("Bound-Range", "#BR", 5)
253        {}
254    };
255
256    class InvalidOpcode : public X86Fault
257    {
258      public:
259        InvalidOpcode() :
260            X86Fault("Invalid-Opcode", "#UD", 6)
261        {}
262    };
263
264    class DeviceNotAvailable : public X86Fault
265    {
266      public:
267        DeviceNotAvailable() :
268            X86Fault("Device-Not-Available", "#NM", 7)
269        {}
270    };
271
272    class DoubleFault : public X86Abort
273    {
274      public:
275        DoubleFault() :
276            X86Abort("Double-Fault", "#DF", 8)
277        {}
278    };
279
280    class InvalidTSS : public X86Fault
281    {
282      public:
283        InvalidTSS() :
284            X86Fault("Invalid-TSS", "#TS", 10)
285        {}
286    };
287
288    class SegmentNotPresent : public X86Fault
289    {
290      public:
291        SegmentNotPresent() :
292            X86Fault("Segment-Not-Present", "#NP", 11)
293        {}
294    };
295
296    class StackFault : public X86Fault
297    {
298      public:
299        StackFault() :
300            X86Fault("Stack", "#SS", 12)
301        {}
302    };
303
304    class GeneralProtection : public X86Fault
305    {
306      public:
307        GeneralProtection(uint64_t _errorCode) :
308            X86Fault("General-Protection", "#GP", 13, _errorCode)
309        {}
310    };
311
312    class PageFault : public X86Fault
313    {
314      public:
315        PageFault() :
316            X86Fault("Page-Fault", "#PF", 14)
317        {}
318    };
319
320    class X87FpExceptionPending : public X86Fault
321    {
322      public:
323        X87FpExceptionPending() :
324            X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
325        {}
326    };
327
328    class AlignmentCheck : public X86Fault
329    {
330      public:
331        AlignmentCheck() :
332            X86Fault("Alignment-Check", "#AC", 17)
333        {}
334    };
335
336    class MachineCheck : public X86Abort
337    {
338      public:
339        MachineCheck() :
340            X86Abort("Machine-Check", "#MC", 18)
341        {}
342    };
343
344    class SIMDFloatingPointFault : public X86Fault
345    {
346      public:
347        SIMDFloatingPointFault() :
348            X86Fault("SIMD Floating-Point", "#XF", 19)
349        {}
350    };
351
352    class SecurityException : public X86FaultBase
353    {
354      public:
355        SecurityException() :
356            X86FaultBase("Security Exception", "#SX", 30)
357        {}
358    };
359
360    class ExternalInterrupt : public X86Interrupt
361    {
362      public:
363        ExternalInterrupt(uint8_t _vector) :
364            X86Interrupt("External Interrupt", "#INTR", _vector)
365        {}
366    };
367
368    class SystemManagementInterrupt : public X86Interrupt
369    {
370      public:
371        SystemManagementInterrupt() :
372            X86Interrupt("System Management Interrupt", "#SMI", 0)
373        {}
374    };
375
376    class InitInterrupt : public X86Interrupt
377    {
378        uint8_t vector;
379      public:
380        InitInterrupt(uint8_t _vector) :
381            X86Interrupt("INIT Interrupt", "#INIT", _vector)
382        {}
383    };
384
385    class SoftwareInterrupt : public X86Interrupt
386    {
387      public:
388        SoftwareInterrupt(uint8_t _vector) :
389            X86Interrupt("Software Interrupt", "INTn", _vector)
390        {}
391    };
392
393    // These faults aren't part of the ISA definition. They trigger filling
394    // the tlb on a miss and are to take the place of a hardware table walker.
395    class FakeITLBFault : public X86Fault
396    {
397      protected:
398        Addr vaddr;
399      public:
400        FakeITLBFault(Addr _vaddr) :
401            X86Fault("fake instruction tlb fault", "itlb", 0),
402            vaddr(_vaddr)
403        {}
404
405        void invoke(ThreadContext * tc);
406    };
407
408    class FakeDTLBFault : public X86Fault
409    {
410      protected:
411        Addr vaddr;
412      public:
413        FakeDTLBFault(Addr _vaddr) :
414            X86Fault("fake data tlb fault", "dtlb", 0),
415            vaddr(_vaddr)
416        {}
417
418        void invoke(ThreadContext * tc);
419    };
420};
421
422#endif // __ARCH_X86_FAULTS_HH__
423