faults.hh revision 5681:54c2d92f601e
12SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 38707Sandreas.hansson@arm.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use of this software in source and binary forms, 68707Sandreas.hansson@arm.com * with or without modification, are permitted provided that the 78707Sandreas.hansson@arm.com * following conditions are met: 88707Sandreas.hansson@arm.com * 98707Sandreas.hansson@arm.com * The software must be used only for Non-Commercial Use which means any 108707Sandreas.hansson@arm.com * use which is NOT directed to receiving any direct monetary 118707Sandreas.hansson@arm.com * compensation for, or commercial advantage from such use. Illustrative 128707Sandreas.hansson@arm.com * examples of non-commercial use are academic research, personal study, 138707Sandreas.hansson@arm.com * teaching, education and corporate research & development. 141762SN/A * Illustrative examples of commercial use are distributing products for 157897Shestness@cs.utexas.edu * commercial advantage and providing services using the software for 162SN/A * commercial advantage. 172SN/A * 182SN/A * If you wish to use this software or functionality therein that may be 192SN/A * covered by patents for commercial use, please contact: 202SN/A * Director of Intellectual Property Licensing 212SN/A * Office of Strategy and Technology 222SN/A * Hewlett-Packard Company 232SN/A * 1501 Page Mill Road 242SN/A * Palo Alto, California 94304 252SN/A * 262SN/A * Redistributions of source code must retain the above copyright notice, 272SN/A * this list of conditions and the following disclaimer. Redistributions 282SN/A * in binary form must reproduce the above copyright notice, this list of 292SN/A * conditions and the following disclaimer in the documentation and/or 302SN/A * other materials provided with the distribution. Neither the name of 312SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 322SN/A * contributors may be used to endorse or promote products derived from 332SN/A * this software without specific prior written permission. No right of 342SN/A * sublicense is granted herewith. Derivatives of the software and 352SN/A * output created using the software may be prepared, but only for 362SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 372SN/A * others provided: (i) the others agree to abide by the list of 382SN/A * conditions herein which includes the Non-Commercial Use restrictions; 392SN/A * and (ii) such Derivatives of the software include the above copyright 402665Ssaidi@eecs.umich.edu * notice to acknowledge the contribution from this software where 412665Ssaidi@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 422665Ssaidi@eecs.umich.edu * 437897Shestness@cs.utexas.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 442SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 452SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 461717SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 471717SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 502SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 519850Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 529850Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 539850Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 549850Sandreas.hansson@arm.com * 559850Sandreas.hansson@arm.com * Authors: Gabe Black 569850Sandreas.hansson@arm.com */ 578745Sgblack@eecs.umich.edu 584182Sgblack@eecs.umich.edu#ifndef __ARCH_X86_FAULTS_HH__ 595664Sgblack@eecs.umich.edu#define __ARCH_X86_FAULTS_HH__ 60707SN/A 618229Snate@binkert.org#include "base/misc.hh" 6256SN/A#include "sim/faults.hh" 638779Sgblack@eecs.umich.edu 644776Sgblack@eecs.umich.edunamespace X86ISA 659814Sandreas.hansson@arm.com{ 662SN/A // Base class for all x86 "faults" where faults is in the m5 sense 678901Sandreas.hansson@arm.com class X86FaultBase : public FaultBase 682315SN/A { 692680Sktlim@umich.edu protected: 702SN/A const char * faultName; 712356SN/A const char * mnem; 722356SN/A uint64_t errorCode; 732356SN/A 746144Sksewell@umich.edu X86FaultBase(const char * _faultName, const char * _mnem, 752356SN/A uint64_t _errorCode = 0) : 762356SN/A faultName(_faultName), mnem(_mnem), errorCode(_errorCode) 776144Sksewell@umich.edu { 782356SN/A } 792356SN/A 806144Sksewell@umich.edu const char * name() const 812356SN/A { 822356SN/A return faultName; 832356SN/A } 846144Sksewell@umich.edu 856144Sksewell@umich.edu virtual bool isBenign() 866144Sksewell@umich.edu { 876144Sksewell@umich.edu return true; 886144Sksewell@umich.edu } 895336Shines@cs.fsu.edu 902356SN/A virtual const char * mnemonic() const 912356SN/A { 922856Srdreslin@umich.edu return mnem; 932SN/A } 941634SN/A }; 959157Sandreas.hansson@arm.com 963814Ssaidi@eecs.umich.edu // Base class for x86 faults which behave as if the underlying instruction 973814Ssaidi@eecs.umich.edu // didn't happen. 985712Shsul@eecs.umich.edu class X86Fault : public X86FaultBase 995712Shsul@eecs.umich.edu { 1005715Shsul@eecs.umich.edu protected: 1015712Shsul@eecs.umich.edu X86Fault(const char * name, const char * mnem, 1025712Shsul@eecs.umich.edu uint64_t _errorCode = 0) : 1031634SN/A X86FaultBase(name, mnem, _errorCode) 10410190Sakash.bagdia@arm.com {} 10510190Sakash.bagdia@arm.com }; 10610190Sakash.bagdia@arm.com 10710190Sakash.bagdia@arm.com // Base class for x86 traps which behave as if the underlying instruction 10810190Sakash.bagdia@arm.com // completed. 10910190Sakash.bagdia@arm.com class X86Trap : public X86FaultBase 11010190Sakash.bagdia@arm.com { 1118832SAli.Saidi@ARM.com protected: 1128832SAli.Saidi@ARM.com X86Trap(const char * name, const char * mnem, 1138832SAli.Saidi@ARM.com uint64_t _errorCode = 0) : 1148832SAli.Saidi@ARM.com X86FaultBase(name, mnem, _errorCode) 1158832SAli.Saidi@ARM.com {} 1168832SAli.Saidi@ARM.com 1179332Sdam.sunwoo@arm.com#if FULL_SYSTEM 1189332Sdam.sunwoo@arm.com void invoke(ThreadContext * tc); 1199332Sdam.sunwoo@arm.com#endif 1209332Sdam.sunwoo@arm.com }; 1219332Sdam.sunwoo@arm.com 1229332Sdam.sunwoo@arm.com // Base class for x86 aborts which seem to be catastrophic failures. 1239332Sdam.sunwoo@arm.com class X86Abort : public X86FaultBase 1249332Sdam.sunwoo@arm.com { 1259332Sdam.sunwoo@arm.com protected: 1269332Sdam.sunwoo@arm.com X86Abort(const char * name, const char * mnem, 1279332Sdam.sunwoo@arm.com uint64_t _errorCode = 0) : 1289430SAndreas.Sandberg@ARM.com X86FaultBase(name, mnem, _errorCode) 1299430SAndreas.Sandberg@ARM.com {} 1309430SAndreas.Sandberg@ARM.com 1319814Sandreas.hansson@arm.com#if FULL_SYSTEM 1329814Sandreas.hansson@arm.com void invoke(ThreadContext * tc); 1339814Sandreas.hansson@arm.com#endif 1341634SN/A }; 1358850Sandreas.hansson@arm.com 1368850Sandreas.hansson@arm.com // Base class for x86 interrupts. 1378850Sandreas.hansson@arm.com class X86Interrupt : public X86FaultBase 1388850Sandreas.hansson@arm.com { 1398850Sandreas.hansson@arm.com protected: 1408850Sandreas.hansson@arm.com uint8_t vector; 1418850Sandreas.hansson@arm.com X86Interrupt(const char * name, const char * mnem, uint8_t _vector, 1429608Sandreas.hansson@arm.com uint64_t _errorCode = 0) : 1438850Sandreas.hansson@arm.com X86FaultBase(name, mnem, _errorCode), vector(_vector) 1448850Sandreas.hansson@arm.com {} 1458850Sandreas.hansson@arm.com 1468850Sandreas.hansson@arm.com#if FULL_SYSTEM 1478850Sandreas.hansson@arm.com void invoke(ThreadContext * tc); 1488850Sandreas.hansson@arm.com#endif 1498850Sandreas.hansson@arm.com }; 1509608Sandreas.hansson@arm.com 1518850Sandreas.hansson@arm.com class UnimpInstFault : public FaultBase 1525712Shsul@eecs.umich.edu { 15310110Sandreas.hansson@arm.com public: 1545712Shsul@eecs.umich.edu const char * name() const 15510190Sakash.bagdia@arm.com { 15610190Sakash.bagdia@arm.com return "unimplemented_micro"; 15710190Sakash.bagdia@arm.com } 1588832SAli.Saidi@ARM.com 1598832SAli.Saidi@ARM.com void invoke(ThreadContext * tc) 1608832SAli.Saidi@ARM.com { 1618832SAli.Saidi@ARM.com panic("Unimplemented instruction!"); 1628832SAli.Saidi@ARM.com } 1638850Sandreas.hansson@arm.com }; 1648926Sandreas.hansson@arm.com 1658926Sandreas.hansson@arm.com static inline Fault genMachineCheckFault() 1668926Sandreas.hansson@arm.com { 1678850Sandreas.hansson@arm.com panic("Machine check fault not implemented in x86!\n"); 1688850Sandreas.hansson@arm.com } 1698850Sandreas.hansson@arm.com 1708850Sandreas.hansson@arm.com // Below is a summary of the interrupt/exception information in the 1718922Swilliam.wang@arm.com // architecture manuals. 1728850Sandreas.hansson@arm.com 1739294Sandreas.hansson@arm.com // Class | Type | vector | Cause | mnem 1749294Sandreas.hansson@arm.com //------------------------------------------------------------------------ 1758850Sandreas.hansson@arm.com //Contrib Fault 0 Divide-by-Zero-Error #DE 1769332Sdam.sunwoo@arm.com //Benign Either 1 Debug #DB 1779332Sdam.sunwoo@arm.com //Benign Interrupt 2 Non-Maskable-Interrupt #NMI 1789332Sdam.sunwoo@arm.com //Benign Trap 3 Breakpoint #BP 1799332Sdam.sunwoo@arm.com //Benign Trap 4 Overflow #OF 1809332Sdam.sunwoo@arm.com //Benign Fault 5 Bound-Range #BR 1819332Sdam.sunwoo@arm.com //Benign Fault 6 Invalid-Opcode #UD 1829332Sdam.sunwoo@arm.com //Benign Fault 7 Device-Not-Available #NM 1839332Sdam.sunwoo@arm.com //Benign Abort 8 Double-Fault #DF 1847914SBrad.Beckmann@amd.com // 9 Coprocessor-Segment-Overrun 1857914SBrad.Beckmann@amd.com //Contrib Fault 10 Invalid-TSS #TS 1863814Ssaidi@eecs.umich.edu //Contrib Fault 11 Segment-Not-Present #NP 1873814Ssaidi@eecs.umich.edu //Contrib Fault 12 Stack #SS 1881634SN/A //Contrib Fault 13 General-Protection #GP 1895664Sgblack@eecs.umich.edu //Either Fault 14 Page-Fault #PF 1905664Sgblack@eecs.umich.edu // 15 Reserved 1912SN/A //Benign Fault 16 x87 Floating-Point Exception Pending #MF 1925704Snate@binkert.org //Benign Fault 17 Alignment-Check #AC 1932SN/A //Benign Abort 18 Machine-Check #MC 1942SN/A //Benign Fault 19 SIMD Floating-Point #XF 1955645Sgblack@eecs.umich.edu // 20-29 Reserved 1965645Sgblack@eecs.umich.edu //Contrib ? 30 Security Exception #SX 1975645Sgblack@eecs.umich.edu // 31 Reserved 1985647Sgblack@eecs.umich.edu //Benign Interrupt 0-255 External Interrupts #INTR 1995645Sgblack@eecs.umich.edu //Benign Interrupt 0-255 Software Interrupts INTn 2005645Sgblack@eecs.umich.edu 2015807Snate@binkert.org class DivideByZero : public X86Fault 2025807Snate@binkert.org { 2035807Snate@binkert.org public: 2045807Snate@binkert.org DivideByZero() : 2055807Snate@binkert.org X86Fault("Divide-by-Zero-Error", "#DE") 2065807Snate@binkert.org {} 2078779Sgblack@eecs.umich.edu }; 2088779Sgblack@eecs.umich.edu 2095807Snate@binkert.org class DebugException : public X86FaultBase 2105807Snate@binkert.org { 2115807Snate@binkert.org public: 2125807Snate@binkert.org DebugException() : 2135807Snate@binkert.org X86FaultBase("Debug", "#DB") 2145807Snate@binkert.org {} 2155807Snate@binkert.org }; 2165807Snate@binkert.org 2175807Snate@binkert.org class NonMaskableInterrupt : public X86Interrupt 2185807Snate@binkert.org { 2195807Snate@binkert.org public: 2205807Snate@binkert.org NonMaskableInterrupt(uint8_t _vector) : 2215807Snate@binkert.org X86Interrupt("Non Maskable Interrupt", "#NMI", _vector) 2222SN/A {} 2235704Snate@binkert.org }; 2245704Snate@binkert.org 2255704Snate@binkert.org class Breakpoint : public X86Trap 2268793Sgblack@eecs.umich.edu { 2275704Snate@binkert.org public: 2281917SN/A Breakpoint() : 2291917SN/A X86Trap("Breakpoint", "#BP") 2301917SN/A {} 2311917SN/A }; 2321917SN/A 2335536Srstrong@hp.com class OverflowTrap : public X86Trap 2341917SN/A { 2351917SN/A public: 2365536Srstrong@hp.com OverflowTrap() : 2371917SN/A X86Trap("Overflow", "#OF") 2381917SN/A {} 2391917SN/A }; 2402SN/A 2412SN/A class BoundRange : public X86Fault 2422680Sktlim@umich.edu { 2432SN/A public: 2444776Sgblack@eecs.umich.edu BoundRange() : 2454776Sgblack@eecs.umich.edu X86Fault("Bound-Range", "#BR") 2462SN/A {} 247393SN/A }; 2487764Sgblack@eecs.umich.edu 2497764Sgblack@eecs.umich.edu class InvalidOpcode : public X86Fault 2507764Sgblack@eecs.umich.edu { 2514776Sgblack@eecs.umich.edu public: 2524776Sgblack@eecs.umich.edu InvalidOpcode() : 2534776Sgblack@eecs.umich.edu X86Fault("Invalid-Opcode", "#UD") 25410407Smitch.hayenga@arm.com {} 25510407Smitch.hayenga@arm.com }; 256393SN/A 257393SN/A class DeviceNotAvailable : public X86Fault 2588737Skoansin.tan@gmail.com { 259393SN/A public: 260393SN/A DeviceNotAvailable() : 2618737Skoansin.tan@gmail.com X86Fault("Device-Not-Available", "#NM") 262393SN/A {} 263393SN/A }; 2648737Skoansin.tan@gmail.com 2652SN/A class DoubleFault : public X86Abort 2664000Ssaidi@eecs.umich.edu { 2674000Ssaidi@eecs.umich.edu public: 2684000Ssaidi@eecs.umich.edu DoubleFault() : 2694000Ssaidi@eecs.umich.edu X86Abort("Double-Fault", "#DF") 2709652SAndreas.Sandberg@ARM.com {} 2714000Ssaidi@eecs.umich.edu }; 27210030SAli.Saidi@ARM.com 27310030SAli.Saidi@ARM.com class InvalidTSS : public X86Fault 27410030SAli.Saidi@ARM.com { 2752SN/A public: 2765529Snate@binkert.org InvalidTSS() : 2775529Snate@binkert.org X86Fault("Invalid-TSS", "#TS") 2785529Snate@binkert.org {} 2798876Sandreas.hansson@arm.com }; 2801191SN/A 2812SN/A class SegmentNotPresent : public X86Fault 2821129SN/A { 2831917SN/A public: 2842SN/A SegmentNotPresent() : 2852SN/A X86Fault("Segment-Not-Present", "#NP") 2862680Sktlim@umich.edu {} 287180SN/A }; 2889254SAndreas.Sandberg@arm.com 2899254SAndreas.Sandberg@arm.com class StackFault : public X86Fault 2909254SAndreas.Sandberg@arm.com { 2919254SAndreas.Sandberg@arm.com public: 2929254SAndreas.Sandberg@arm.com StackFault() : 2939254SAndreas.Sandberg@arm.com X86Fault("Stack", "#SS") 2949254SAndreas.Sandberg@arm.com {} 2952798Sktlim@umich.edu }; 296180SN/A 2979254SAndreas.Sandberg@arm.com class GeneralProtection : public X86Fault 2989254SAndreas.Sandberg@arm.com { 2999254SAndreas.Sandberg@arm.com public: 3009254SAndreas.Sandberg@arm.com GeneralProtection(uint64_t _errorCode) : 3019254SAndreas.Sandberg@arm.com X86Fault("General-Protection", "#GP", _errorCode) 3029254SAndreas.Sandberg@arm.com {} 3039254SAndreas.Sandberg@arm.com }; 3049254SAndreas.Sandberg@arm.com 3059254SAndreas.Sandberg@arm.com class PageFault : public X86Fault 3069254SAndreas.Sandberg@arm.com { 3079254SAndreas.Sandberg@arm.com public: 3089254SAndreas.Sandberg@arm.com PageFault() : 309180SN/A X86Fault("Page-Fault", "#PF") 310124SN/A {} 3119446SAndreas.Sandberg@ARM.com }; 3129446SAndreas.Sandberg@ARM.com 3139446SAndreas.Sandberg@ARM.com class X87FpExceptionPending : public X86Fault 3149446SAndreas.Sandberg@ARM.com { 3159446SAndreas.Sandberg@ARM.com public: 3169446SAndreas.Sandberg@ARM.com X87FpExceptionPending() : 3179446SAndreas.Sandberg@ARM.com X86Fault("x87 Floating-Point Exception Pending", "#MF") 3189446SAndreas.Sandberg@ARM.com {} 3199446SAndreas.Sandberg@ARM.com }; 3209446SAndreas.Sandberg@ARM.com 3219446SAndreas.Sandberg@ARM.com class AlignmentCheck : public X86Fault 3229430SAndreas.Sandberg@ARM.com { 3239430SAndreas.Sandberg@ARM.com public: 3249430SAndreas.Sandberg@ARM.com AlignmentCheck() : 3259430SAndreas.Sandberg@ARM.com X86Fault("Alignment-Check", "#AC") 3269430SAndreas.Sandberg@ARM.com {} 3279430SAndreas.Sandberg@ARM.com }; 3289430SAndreas.Sandberg@ARM.com 3299523SAndreas.Sandberg@ARM.com class MachineCheck : public X86Abort 3309523SAndreas.Sandberg@ARM.com { 3319523SAndreas.Sandberg@ARM.com public: 3329523SAndreas.Sandberg@ARM.com MachineCheck() : 3339523SAndreas.Sandberg@ARM.com X86Abort("Machine-Check", "#MC") 3349523SAndreas.Sandberg@ARM.com {} 3359523SAndreas.Sandberg@ARM.com }; 3369523SAndreas.Sandberg@ARM.com 3379523SAndreas.Sandberg@ARM.com class SIMDFloatingPointFault : public X86Fault 3389523SAndreas.Sandberg@ARM.com { 3399523SAndreas.Sandberg@ARM.com public: 340124SN/A SIMDFloatingPointFault() : 341124SN/A X86Fault("SIMD Floating-Point", "#XF") 342124SN/A {} 3436221Snate@binkert.org }; 3442SN/A 345124SN/A class SecurityException : public X86FaultBase 346124SN/A { 347124SN/A public: 348124SN/A SecurityException() : 349124SN/A X86FaultBase("Security Exception", "#SX") 350503SN/A {} 3512SN/A }; 352124SN/A 353124SN/A class ExternalInterrupt : public X86Interrupt 354124SN/A { 355124SN/A public: 356124SN/A ExternalInterrupt(uint8_t _vector) : 357124SN/A X86Interrupt("External Interrupt", "#INTR", _vector) 358124SN/A {} 3592SN/A }; 360921SN/A 361921SN/A class SystemManagementInterrupt : public X86Interrupt 3629814Sandreas.hansson@arm.com { 3639814Sandreas.hansson@arm.com public: 3649814Sandreas.hansson@arm.com SystemManagementInterrupt() : 3659814Sandreas.hansson@arm.com X86Interrupt("System Management Interrupt", "#SMI", 0) 3669814Sandreas.hansson@arm.com {} 367921SN/A }; 3689448SAndreas.Sandberg@ARM.com 3699448SAndreas.Sandberg@ARM.com class InitInterrupt : public X86Interrupt 3709448SAndreas.Sandberg@ARM.com { 3719448SAndreas.Sandberg@ARM.com uint8_t vector; 3729448SAndreas.Sandberg@ARM.com public: 3739448SAndreas.Sandberg@ARM.com InitInterrupt(uint8_t _vector) : 374921SN/A X86Interrupt("INIT Interrupt", "#INIT", _vector) 375921SN/A {} 376921SN/A }; 377921SN/A 378921SN/A class SoftwareInterrupt : public X86Interrupt 379921SN/A { 3809448SAndreas.Sandberg@ARM.com public: 3819448SAndreas.Sandberg@ARM.com SoftwareInterrupt(uint8_t _vector) : 3829448SAndreas.Sandberg@ARM.com X86Interrupt("Software Interrupt", "INTn", _vector) 3839448SAndreas.Sandberg@ARM.com {} 3849448SAndreas.Sandberg@ARM.com }; 3859448SAndreas.Sandberg@ARM.com 386921SN/A // These faults aren't part of the ISA definition. They trigger filling 3879448SAndreas.Sandberg@ARM.com // the tlb on a miss and are to take the place of a hardware table walker. 388921SN/A class FakeITLBFault : public X86Fault 389921SN/A { 390921SN/A protected: 391124SN/A Addr vaddr; 3929448SAndreas.Sandberg@ARM.com public: 3939448SAndreas.Sandberg@ARM.com FakeITLBFault(Addr _vaddr) : 3949448SAndreas.Sandberg@ARM.com X86Fault("fake instruction tlb fault", "itlb"), 3959448SAndreas.Sandberg@ARM.com vaddr(_vaddr) 3969448SAndreas.Sandberg@ARM.com {} 3979448SAndreas.Sandberg@ARM.com 3989448SAndreas.Sandberg@ARM.com void invoke(ThreadContext * tc); 3999448SAndreas.Sandberg@ARM.com }; 4009448SAndreas.Sandberg@ARM.com 4019448SAndreas.Sandberg@ARM.com class FakeDTLBFault : public X86Fault 4029448SAndreas.Sandberg@ARM.com { 4039448SAndreas.Sandberg@ARM.com protected: 4049448SAndreas.Sandberg@ARM.com Addr vaddr; 4059448SAndreas.Sandberg@ARM.com public: 4069448SAndreas.Sandberg@ARM.com FakeDTLBFault(Addr _vaddr) : 4079448SAndreas.Sandberg@ARM.com X86Fault("fake data tlb fault", "dtlb"), 4089448SAndreas.Sandberg@ARM.com vaddr(_vaddr) 4098834Satgutier@umich.edu {} 4108834Satgutier@umich.edu 4118834Satgutier@umich.edu void invoke(ThreadContext * tc); 412707SN/A }; 4139749Sandreas@sandberg.pp.se}; 4149749Sandreas@sandberg.pp.se 4159749Sandreas@sandberg.pp.se#endif // __ARCH_X86_FAULTS_HH__ 4169749Sandreas@sandberg.pp.se