faults.cc revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "base/trace.hh"
46#include "config/full_system.hh"
47#include "cpu/thread_context.hh"
48
49#if !FULL_SYSTEM
50#include "arch/x86/isa_traits.hh"
51#include "mem/page_table.hh"
52#include "sim/process.hh"
53#else
54#include "arch/x86/tlb.hh"
55#include "debug/Faults.hh"
56#endif
57
58namespace X86ISA
59{
60#if FULL_SYSTEM
61    void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
62    {
63        PCState pcState = tc->pcState();
64        Addr pc = pcState.pc();
65        DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
66        using namespace X86ISAInst::RomLabels;
67        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
68        MicroPC entry;
69        if (m5reg.mode == LongMode) {
70            if (isSoft()) {
71                entry = extern_label_longModeSoftInterrupt;
72            } else {
73                entry = extern_label_longModeInterrupt;
74            }
75        } else {
76            entry = extern_label_legacyModeInterrupt;
77        }
78        tc->setIntReg(INTREG_MICRO(1), vector);
79        tc->setIntReg(INTREG_MICRO(7), pc);
80        if (errorCode != (uint64_t)(-1)) {
81            if (m5reg.mode == LongMode) {
82                entry = extern_label_longModeInterruptWithError;
83            } else {
84                panic("Legacy mode interrupts with error codes "
85                        "aren't implementde.\n");
86            }
87            // Software interrupts shouldn't have error codes. If one does,
88            // there would need to be microcode to set it up.
89            assert(!isSoft());
90            tc->setIntReg(INTREG_MICRO(15), errorCode);
91        }
92        pcState.upc(romMicroPC(entry));
93        pcState.nupc(romMicroPC(entry) + 1);
94        tc->pcState(pcState);
95    }
96
97    std::string
98    X86FaultBase::describe() const
99    {
100        std::stringstream ss;
101        ccprintf(ss, "%s", mnemonic());
102        if (errorCode != (uint64_t)(-1)) {
103            ccprintf(ss, "(%#x)", errorCode);
104        }
105
106        return ss.str();
107    }
108
109    void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
110    {
111        X86FaultBase::invoke(tc);
112        // This is the same as a fault, but it happens -after- the instruction.
113        PCState pc = tc->pcState();
114        pc.uEnd();
115    }
116
117    void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
118    {
119        panic("Abort exception!");
120    }
121
122    void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
123    {
124        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
125        X86FaultBase::invoke(tc);
126        /*
127         * If something bad happens while trying to enter the page fault
128         * handler, I'm pretty sure that's a double fault and then all bets are
129         * off. That means it should be safe to update this state now.
130         */
131        if (m5reg.mode == LongMode) {
132            tc->setMiscReg(MISCREG_CR2, addr);
133        } else {
134            tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
135        }
136    }
137
138    std::string
139    PageFault::describe() const
140    {
141        std::stringstream ss;
142        ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
143        return ss.str();
144    }
145
146    void
147    InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
148    {
149        DPRINTF(Faults, "Init interrupt.\n");
150        // The otherwise unmodified integer registers should be set to 0.
151        for (int index = 0; index < NUM_INTREGS; index++) {
152            tc->setIntReg(index, 0);
153        }
154
155        CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
156        CR0 newCR0 = 1 << 4;
157        newCR0.cd = cr0.cd;
158        newCR0.nw = cr0.nw;
159        tc->setMiscReg(MISCREG_CR0, newCR0);
160        tc->setMiscReg(MISCREG_CR2, 0);
161        tc->setMiscReg(MISCREG_CR3, 0);
162        tc->setMiscReg(MISCREG_CR4, 0);
163
164        tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
165
166        tc->setMiscReg(MISCREG_EFER, 0);
167
168        SegAttr dataAttr = 0;
169        dataAttr.dpl = 0;
170        dataAttr.unusable = 0;
171        dataAttr.defaultSize = 0;
172        dataAttr.longMode = 0;
173        dataAttr.avl = 0;
174        dataAttr.granularity = 0;
175        dataAttr.present = 1;
176        dataAttr.type = 3;
177        dataAttr.writable = 1;
178        dataAttr.readable = 1;
179        dataAttr.expandDown = 0;
180        dataAttr.system = 1;
181
182        for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
183            tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
184            tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
185            tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
186            tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
187            tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
188        }
189
190        SegAttr codeAttr = 0;
191        codeAttr.dpl = 0;
192        codeAttr.unusable = 0;
193        codeAttr.defaultSize = 0;
194        codeAttr.longMode = 0;
195        codeAttr.avl = 0;
196        codeAttr.granularity = 0;
197        codeAttr.present = 1;
198        codeAttr.type = 10;
199        codeAttr.writable = 0;
200        codeAttr.readable = 1;
201        codeAttr.expandDown = 0;
202        codeAttr.system = 1;
203
204        tc->setMiscReg(MISCREG_CS, 0xf000);
205        tc->setMiscReg(MISCREG_CS_BASE,
206                0x00000000ffff0000ULL);
207        tc->setMiscReg(MISCREG_CS_EFF_BASE,
208                0x00000000ffff0000ULL);
209        // This has the base value pre-added.
210        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
211        tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
212
213        PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
214        tc->pcState(pc);
215
216        tc->setMiscReg(MISCREG_TSG_BASE, 0);
217        tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
218
219        tc->setMiscReg(MISCREG_IDTR_BASE, 0);
220        tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
221
222        tc->setMiscReg(MISCREG_TSL, 0);
223        tc->setMiscReg(MISCREG_TSL_BASE, 0);
224        tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
225        tc->setMiscReg(MISCREG_TSL_ATTR, 0);
226
227        tc->setMiscReg(MISCREG_TR, 0);
228        tc->setMiscReg(MISCREG_TR_BASE, 0);
229        tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
230        tc->setMiscReg(MISCREG_TR_ATTR, 0);
231
232        // This value should be the family/model/stepping of the processor.
233        // (page 418). It should be consistent with the value from CPUID, but
234        // the actual value probably doesn't matter much.
235        tc->setIntReg(INTREG_RDX, 0);
236
237        tc->setMiscReg(MISCREG_DR0, 0);
238        tc->setMiscReg(MISCREG_DR1, 0);
239        tc->setMiscReg(MISCREG_DR2, 0);
240        tc->setMiscReg(MISCREG_DR3, 0);
241
242        tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
243        tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
244
245        // Update the handy M5 Reg.
246        tc->setMiscReg(MISCREG_M5_REG, 0);
247        MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
248        pc.upc(romMicroPC(entry));
249        pc.nupc(romMicroPC(entry) + 1);
250        tc->pcState(pc);
251    }
252
253    void
254    StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
255    {
256        DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
257        HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
258        if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
259            panic("Startup IPI recived outside of real mode. "
260                    "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
261        }
262
263        tc->setMiscReg(MISCREG_CS, vector << 8);
264        tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
265        tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
266        // This has the base value pre-added.
267        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
268
269        tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
270    }
271
272#else
273
274    void
275    InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
276    {
277        panic("Unrecognized/invalid instruction executed:\n %s",
278                inst->machInst);
279    }
280
281    void
282    PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
283    {
284        PageFaultErrorCode code = errorCode;
285        const char *modeStr = "";
286        if (code.fetch)
287            modeStr = "execute";
288        else if (code.write)
289            modeStr = "write";
290        else
291            modeStr = "read";
292        panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
293    }
294
295#endif
296} // namespace X86ISA
297
298