faults.cc revision 6048:65a321a3a691 
1/*
2 * Copyright (c) 2003-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31/*
32 * Copyright (c) 2007 The Hewlett-Packard Development Company
33 * All rights reserved.
34 *
35 * Redistribution and use of this software in source and binary forms,
36 * with or without modification, are permitted provided that the
37 * following conditions are met:
38 *
39 * The software must be used only for Non-Commercial Use which means any
40 * use which is NOT directed to receiving any direct monetary
41 * compensation for, or commercial advantage from such use.  Illustrative
42 * examples of non-commercial use are academic research, personal study,
43 * teaching, education and corporate research & development.
44 * Illustrative examples of commercial use are distributing products for
45 * commercial advantage and providing services using the software for
46 * commercial advantage.
47 *
48 * If you wish to use this software or functionality therein that may be
49 * covered by patents for commercial use, please contact:
50 *     Director of Intellectual Property Licensing
51 *     Office of Strategy and Technology
52 *     Hewlett-Packard Company
53 *     1501 Page Mill Road
54 *     Palo Alto, California  94304
55 *
56 * Redistributions of source code must retain the above copyright notice,
57 * this list of conditions and the following disclaimer.  Redistributions
58 * in binary form must reproduce the above copyright notice, this list of
59 * conditions and the following disclaimer in the documentation and/or
60 * other materials provided with the distribution.  Neither the name of
61 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
62 * contributors may be used to endorse or promote products derived from
63 * this software without specific prior written permission.  No right of
64 * sublicense is granted herewith.  Derivatives of the software and
65 * output created using the software may be prepared, but only for
66 * Non-Commercial Uses.  Derivatives of the software may be shared with
67 * others provided: (i) the others agree to abide by the list of
68 * conditions herein which includes the Non-Commercial Use restrictions;
69 * and (ii) such Derivatives of the software include the above copyright
70 * notice to acknowledge the contribution from this software where
71 * applicable, this list of conditions and the disclaimer below.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
74 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
75 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
76 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
77 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
79 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
80 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
81 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
82 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 *
85 * Authors: Gabe Black
86 */
87
88#include "arch/x86/decoder.hh"
89#include "arch/x86/faults.hh"
90#include "base/trace.hh"
91#include "config/full_system.hh"
92#include "cpu/thread_context.hh"
93#if !FULL_SYSTEM
94#include "arch/x86/isa_traits.hh"
95#include "mem/page_table.hh"
96#include "sim/process.hh"
97#else
98#include "arch/x86/tlb.hh"
99#endif
100
101namespace X86ISA
102{
103#if FULL_SYSTEM
104    void X86FaultBase::invoke(ThreadContext * tc)
105    {
106        Addr pc = tc->readPC();
107        DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
108        using namespace X86ISAInst::RomLabels;
109        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
110        MicroPC entry;
111        if (m5reg.mode == LongMode) {
112            if (isSoft()) {
113                entry = extern_label_longModeSoftInterrupt;
114            } else {
115                entry = extern_label_longModeInterrupt;
116            }
117        } else {
118            entry = extern_label_legacyModeInterrupt;
119        }
120        tc->setIntReg(INTREG_MICRO(1), vector);
121        tc->setIntReg(INTREG_MICRO(7), pc);
122        if (errorCode != (uint64_t)(-1)) {
123            if (m5reg.mode == LongMode) {
124                entry = extern_label_longModeInterruptWithError;
125            } else {
126                panic("Legacy mode interrupts with error codes "
127                        "aren't implementde.\n");
128            }
129            // Software interrupts shouldn't have error codes. If one does,
130            // there would need to be microcode to set it up.
131            assert(!isSoft());
132            tc->setIntReg(INTREG_MICRO(15), errorCode);
133        }
134        tc->setMicroPC(romMicroPC(entry));
135        tc->setNextMicroPC(romMicroPC(entry) + 1);
136    }
137
138    std::string
139    X86FaultBase::describe() const
140    {
141        std::stringstream ss;
142        ccprintf(ss, "%s", mnemonic());
143        if (errorCode != (uint64_t)(-1)) {
144            ccprintf(ss, "(%#x)", errorCode);
145        }
146
147        return ss.str();
148    }
149
150    void X86Trap::invoke(ThreadContext * tc)
151    {
152        X86FaultBase::invoke(tc);
153        // This is the same as a fault, but it happens -after- the instruction.
154        tc->setPC(tc->readNextPC());
155        tc->setNextPC(tc->readNextNPC());
156        tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
157    }
158
159    void X86Abort::invoke(ThreadContext * tc)
160    {
161        panic("Abort exception!");
162    }
163
164    void PageFault::invoke(ThreadContext * tc)
165    {
166        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
167        X86FaultBase::invoke(tc);
168        /*
169         * If something bad happens while trying to enter the page fault
170         * handler, I'm pretty sure that's a double fault and then all bets are
171         * off. That means it should be safe to update this state now.
172         */
173        if (m5reg.mode == LongMode) {
174            tc->setMiscReg(MISCREG_CR2, addr);
175        } else {
176            tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
177        }
178    }
179
180    std::string
181    PageFault::describe() const
182    {
183        std::stringstream ss;
184        ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
185        return ss.str();
186    }
187
188    void
189    InitInterrupt::invoke(ThreadContext *tc)
190    {
191        DPRINTF(Faults, "Init interrupt.\n");
192        // The otherwise unmodified integer registers should be set to 0.
193        for (int index = 0; index < NUM_INTREGS; index++) {
194            tc->setIntReg(index, 0);
195        }
196
197        CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
198        CR0 newCR0 = 1 << 4;
199        newCR0.cd = cr0.cd;
200        newCR0.nw = cr0.nw;
201        tc->setMiscReg(MISCREG_CR0, newCR0);
202        tc->setMiscReg(MISCREG_CR2, 0);
203        tc->setMiscReg(MISCREG_CR3, 0);
204        tc->setMiscReg(MISCREG_CR4, 0);
205
206        tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
207
208        tc->setMiscReg(MISCREG_EFER, 0);
209
210        SegAttr dataAttr = 0;
211        dataAttr.writable = 1;
212        dataAttr.readable = 1;
213        dataAttr.expandDown = 0;
214        dataAttr.dpl = 0;
215        dataAttr.defaultSize = 0;
216
217        for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
218            tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
219            tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
220            tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
221            tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
222            tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
223        }
224
225        SegAttr codeAttr = 0;
226        codeAttr.writable = 0;
227        codeAttr.readable = 1;
228        codeAttr.expandDown = 0;
229        codeAttr.dpl = 0;
230        codeAttr.defaultSize = 0;
231
232        tc->setMiscReg(MISCREG_CS, 0xf000);
233        tc->setMiscReg(MISCREG_CS_BASE,
234                0x00000000ffff0000ULL);
235        tc->setMiscReg(MISCREG_CS_EFF_BASE,
236                0x00000000ffff0000ULL);
237        // This has the base value pre-added.
238        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
239        tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
240
241        tc->setPC(0x000000000000fff0ULL +
242                tc->readMiscReg(MISCREG_CS_BASE));
243        tc->setNextPC(tc->readPC() + sizeof(MachInst));
244
245        tc->setMiscReg(MISCREG_TSG_BASE, 0);
246        tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
247
248        tc->setMiscReg(MISCREG_IDTR_BASE, 0);
249        tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
250
251        tc->setMiscReg(MISCREG_TSL, 0);
252        tc->setMiscReg(MISCREG_TSL_BASE, 0);
253        tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
254        tc->setMiscReg(MISCREG_TSL_ATTR, 0);
255
256        tc->setMiscReg(MISCREG_TR, 0);
257        tc->setMiscReg(MISCREG_TR_BASE, 0);
258        tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
259        tc->setMiscReg(MISCREG_TR_ATTR, 0);
260
261        // This value should be the family/model/stepping of the processor.
262        // (page 418). It should be consistent with the value from CPUID, but
263        // the actual value probably doesn't matter much.
264        tc->setIntReg(INTREG_RDX, 0);
265
266        tc->setMiscReg(MISCREG_DR0, 0);
267        tc->setMiscReg(MISCREG_DR1, 0);
268        tc->setMiscReg(MISCREG_DR2, 0);
269        tc->setMiscReg(MISCREG_DR3, 0);
270
271        tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
272        tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
273
274        // We're now in real mode, effectively at CPL 0
275        HandyM5Reg m5Reg = 0;
276        m5Reg.mode = LegacyMode;
277        m5Reg.submode = RealMode;
278        m5Reg.cpl = 0;
279        tc->setMiscReg(MISCREG_M5_REG, m5Reg);
280        MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
281        tc->setMicroPC(romMicroPC(entry));
282        tc->setNextMicroPC(romMicroPC(entry) + 1);
283    }
284
285#endif
286} // namespace X86ISA
287
288