faults.cc revision 5909
110623Smitch.hayenga@arm.com/* 29288Sandreas.hansson@arm.com * Copyright (c) 2003-2007 The Regents of The University of Michigan 39288Sandreas.hansson@arm.com * All rights reserved. 49288Sandreas.hansson@arm.com * 59288Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 69288Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 79288Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 89288Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 99288Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 109288Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 119288Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 129288Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 139288Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 149288Sandreas.hansson@arm.com * this software without specific prior written permission. 159288Sandreas.hansson@arm.com * 169288Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179288Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189288Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199288Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209288Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219288Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229288Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239288Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249288Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259288Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269288Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279288Sandreas.hansson@arm.com * 289288Sandreas.hansson@arm.com * Authors: Gabe Black 299288Sandreas.hansson@arm.com */ 309288Sandreas.hansson@arm.com 319288Sandreas.hansson@arm.com/* 329288Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 339288Sandreas.hansson@arm.com * All rights reserved. 349288Sandreas.hansson@arm.com * 359288Sandreas.hansson@arm.com * Redistribution and use of this software in source and binary forms, 369288Sandreas.hansson@arm.com * with or without modification, are permitted provided that the 379288Sandreas.hansson@arm.com * following conditions are met: 389288Sandreas.hansson@arm.com * 399288Sandreas.hansson@arm.com * The software must be used only for Non-Commercial Use which means any 4010623Smitch.hayenga@arm.com * use which is NOT directed to receiving any direct monetary 419288Sandreas.hansson@arm.com * compensation for, or commercial advantage from such use. Illustrative 429288Sandreas.hansson@arm.com * examples of non-commercial use are academic research, personal study, 4313416Sjavier.bueno@metempsy.com * teaching, education and corporate research & development. 448831Smrinmoy.ghosh@arm.com * Illustrative examples of commercial use are distributing products for 458832SAli.Saidi@ARM.com * commercial advantage and providing services using the software for 4613427Sodanrc@yahoo.com.br * commercial advantage. 478832SAli.Saidi@ARM.com * 4813416Sjavier.bueno@metempsy.com * If you wish to use this software or functionality therein that may be 4913416Sjavier.bueno@metempsy.com * covered by patents for commercial use, please contact: 5013416Sjavier.bueno@metempsy.com * Director of Intellectual Property Licensing 5113416Sjavier.bueno@metempsy.com * Office of Strategy and Technology 5213416Sjavier.bueno@metempsy.com * Hewlett-Packard Company 5313416Sjavier.bueno@metempsy.com * 1501 Page Mill Road 5413416Sjavier.bueno@metempsy.com * Palo Alto, California 94304 5513416Sjavier.bueno@metempsy.com * 5613416Sjavier.bueno@metempsy.com * Redistributions of source code must retain the above copyright notice, 5713416Sjavier.bueno@metempsy.com * this list of conditions and the following disclaimer. Redistributions 5813416Sjavier.bueno@metempsy.com * in binary form must reproduce the above copyright notice, this list of 5913416Sjavier.bueno@metempsy.com * conditions and the following disclaimer in the documentation and/or 609288Sandreas.hansson@arm.com * other materials provided with the distribution. Neither the name of 618831Smrinmoy.ghosh@arm.com * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 628831Smrinmoy.ghosh@arm.com * contributors may be used to endorse or promote products derived from 639338SAndreas.Sandberg@arm.com * this software without specific prior written permission. No right of 6413416Sjavier.bueno@metempsy.com * sublicense is granted herewith. Derivatives of the software and 6513416Sjavier.bueno@metempsy.com * output created using the software may be prepared, but only for 6613416Sjavier.bueno@metempsy.com * Non-Commercial Uses. Derivatives of the software may be shared with 6710466Sandreas.hansson@arm.com * others provided: (i) the others agree to abide by the list of 688831Smrinmoy.ghosh@arm.com * conditions herein which includes the Non-Commercial Use restrictions; 6913422Sodanrc@yahoo.com.br * and (ii) such Derivatives of the software include the above copyright 7013422Sodanrc@yahoo.com.br * notice to acknowledge the contribution from this software where 7113422Sodanrc@yahoo.com.br * applicable, this list of conditions and the disclaimer below. 7210623Smitch.hayenga@arm.com * 7310623Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 7410623Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 7510623Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 7610623Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 7713416Sjavier.bueno@metempsy.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 7813416Sjavier.bueno@metempsy.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 7913551Sjavier.bueno@metempsy.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 8013551Sjavier.bueno@metempsy.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 8113416Sjavier.bueno@metempsy.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 8213416Sjavier.bueno@metempsy.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 8313416Sjavier.bueno@metempsy.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 8413416Sjavier.bueno@metempsy.com * 8513416Sjavier.bueno@metempsy.com * Authors: Gabe Black 8613416Sjavier.bueno@metempsy.com */ 8713416Sjavier.bueno@metempsy.com 8813416Sjavier.bueno@metempsy.com#include "arch/x86/decoder.hh" 8913416Sjavier.bueno@metempsy.com#include "arch/x86/faults.hh" 9013416Sjavier.bueno@metempsy.com#include "base/trace.hh" 9113416Sjavier.bueno@metempsy.com#include "config/full_system.hh" 9213416Sjavier.bueno@metempsy.com#include "cpu/thread_context.hh" 9313416Sjavier.bueno@metempsy.com#if !FULL_SYSTEM 9413416Sjavier.bueno@metempsy.com#include "arch/x86/isa_traits.hh" 9513416Sjavier.bueno@metempsy.com#include "mem/page_table.hh" 9613416Sjavier.bueno@metempsy.com#include "sim/process.hh" 9713416Sjavier.bueno@metempsy.com#else 9813416Sjavier.bueno@metempsy.com#include "arch/x86/tlb.hh" 9910623Smitch.hayenga@arm.com#endif 10010623Smitch.hayenga@arm.com 10110623Smitch.hayenga@arm.comnamespace X86ISA 10210623Smitch.hayenga@arm.com{ 10310623Smitch.hayenga@arm.com#if FULL_SYSTEM 10410623Smitch.hayenga@arm.com void X86FaultBase::invoke(ThreadContext * tc) 10510623Smitch.hayenga@arm.com { 10610623Smitch.hayenga@arm.com Addr pc = tc->readPC(); 10710623Smitch.hayenga@arm.com DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe()); 10810623Smitch.hayenga@arm.com using namespace X86ISAInst::RomLabels; 10910623Smitch.hayenga@arm.com HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 11010623Smitch.hayenga@arm.com MicroPC entry; 11110623Smitch.hayenga@arm.com if (m5reg.mode == LongMode) { 11210623Smitch.hayenga@arm.com if (isSoft()) { 11310623Smitch.hayenga@arm.com entry = extern_label_longModeSoftInterrupt; 1148831Smrinmoy.ghosh@arm.com } else { 1158831Smrinmoy.ghosh@arm.com entry = extern_label_longModeInterrupt; 1169338SAndreas.Sandberg@arm.com } 1178831Smrinmoy.ghosh@arm.com } else { 11813422Sodanrc@yahoo.com.br entry = extern_label_legacyModeInterrupt; 11913422Sodanrc@yahoo.com.br } 12013422Sodanrc@yahoo.com.br tc->setIntReg(INTREG_MICRO(1), vector); 12110623Smitch.hayenga@arm.com tc->setIntReg(INTREG_MICRO(7), pc); 12210623Smitch.hayenga@arm.com if (errorCode != (uint64_t)(-1)) { 12310623Smitch.hayenga@arm.com if (m5reg.mode == LongMode) { 12410623Smitch.hayenga@arm.com entry = extern_label_longModeInterruptWithError; 12510623Smitch.hayenga@arm.com } else { 12610623Smitch.hayenga@arm.com panic("Legacy mode interrupts with error codes " 12710623Smitch.hayenga@arm.com "aren't implementde.\n"); 12810623Smitch.hayenga@arm.com } 12910623Smitch.hayenga@arm.com // Software interrupts shouldn't have error codes. If one does, 13010623Smitch.hayenga@arm.com // there would need to be microcode to set it up. 13110623Smitch.hayenga@arm.com assert(!isSoft()); 13213427Sodanrc@yahoo.com.br tc->setIntReg(INTREG_MICRO(15), errorCode); 13313427Sodanrc@yahoo.com.br } 13413427Sodanrc@yahoo.com.br tc->setMicroPC(romMicroPC(entry)); 13513427Sodanrc@yahoo.com.br tc->setNextMicroPC(romMicroPC(entry) + 1); 13610623Smitch.hayenga@arm.com } 1378831Smrinmoy.ghosh@arm.com 1388831Smrinmoy.ghosh@arm.com std::string 1399338SAndreas.Sandberg@arm.com X86FaultBase::describe() const 1408831Smrinmoy.ghosh@arm.com { 14110623Smitch.hayenga@arm.com std::stringstream ss; 142 ccprintf(ss, "%s", mnemonic()); 143 if (errorCode != (uint64_t)(-1)) { 144 ccprintf(ss, "(%#x)", errorCode); 145 } 146 147 return ss.str(); 148 } 149 150 void X86Trap::invoke(ThreadContext * tc) 151 { 152 X86FaultBase::invoke(tc); 153 // This is the same as a fault, but it happens -after- the instruction. 154 tc->setPC(tc->readNextPC()); 155 tc->setNextPC(tc->readNextNPC()); 156 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); 157 } 158 159 void X86Abort::invoke(ThreadContext * tc) 160 { 161 panic("Abort exception!"); 162 } 163 164 void PageFault::invoke(ThreadContext * tc) 165 { 166 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 167 X86FaultBase::invoke(tc); 168 /* 169 * If something bad happens while trying to enter the page fault 170 * handler, I'm pretty sure that's a double fault and then all bets are 171 * off. That means it should be safe to update this state now. 172 */ 173 if (m5reg.mode == LongMode) { 174 tc->setMiscReg(MISCREG_CR2, addr); 175 } else { 176 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 177 } 178 } 179 180 std::string 181 PageFault::describe() const 182 { 183 std::stringstream ss; 184 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); 185 return ss.str(); 186 } 187 188#endif 189} // namespace X86ISA 190 191