faults.cc revision 11793
15124Sgblack@eecs.umich.edu/*
27087Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company
37087Snate@binkert.org * All rights reserved.
47087Snate@binkert.org *
57087Snate@binkert.org * The license below extends only to copyright in the software and shall
67087Snate@binkert.org * not be construed as granting a license to any other intellectual
77087Snate@binkert.org * property including but not limited to intellectual property relating
87087Snate@binkert.org * to a hardware implementation of the functionality of the software
97087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
127087Snate@binkert.org * modified or unmodified, in source code or in binary form.
137087Snate@binkert.org *
145124Sgblack@eecs.umich.edu * Copyright (c) 2003-2007 The Regents of The University of Michigan
155124Sgblack@eecs.umich.edu * All rights reserved.
165124Sgblack@eecs.umich.edu *
175124Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
185124Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
195124Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
205124Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
215124Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
225124Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
235124Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
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255124Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
265124Sgblack@eecs.umich.edu * this software without specific prior written permission.
275124Sgblack@eecs.umich.edu *
285124Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
295124Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
305124Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
315124Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
325124Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
335124Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
345124Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
355124Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
365124Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
375124Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
385124Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
395124Sgblack@eecs.umich.edu *
405124Sgblack@eecs.umich.edu * Authors: Gabe Black
415124Sgblack@eecs.umich.edu */
425124Sgblack@eecs.umich.edu
4311793Sbrandon.potter@amd.com#include "arch/x86/faults.hh"
4411793Sbrandon.potter@amd.com
458961Sgblack@eecs.umich.edu#include "arch/x86/generated/decoder.hh"
468740Sgblack@eecs.umich.edu#include "arch/x86/isa_traits.hh"
475124Sgblack@eecs.umich.edu#include "base/trace.hh"
485124Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
498232Snate@binkert.org#include "debug/Faults.hh"
508740Sgblack@eecs.umich.edu#include "sim/full_system.hh"
515124Sgblack@eecs.umich.edu
525124Sgblack@eecs.umich.edunamespace X86ISA
535124Sgblack@eecs.umich.edu{
5410417Sandreas.hansson@arm.com    void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
555124Sgblack@eecs.umich.edu    {
568806Sgblack@eecs.umich.edu        if (!FullSystem) {
578806Sgblack@eecs.umich.edu            FaultBase::invoke(tc, inst);
588806Sgblack@eecs.umich.edu            return;
598806Sgblack@eecs.umich.edu        }
608806Sgblack@eecs.umich.edu
618806Sgblack@eecs.umich.edu        PCState pcState = tc->pcState();
628806Sgblack@eecs.umich.edu        Addr pc = pcState.pc();
638806Sgblack@eecs.umich.edu        DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
648806Sgblack@eecs.umich.edu                pc, vector, describe());
658806Sgblack@eecs.umich.edu        using namespace X86ISAInst::RomLabels;
668806Sgblack@eecs.umich.edu        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
678806Sgblack@eecs.umich.edu        MicroPC entry;
688806Sgblack@eecs.umich.edu        if (m5reg.mode == LongMode) {
698806Sgblack@eecs.umich.edu            if (isSoft()) {
708806Sgblack@eecs.umich.edu                entry = extern_label_longModeSoftInterrupt;
718806Sgblack@eecs.umich.edu            } else {
728806Sgblack@eecs.umich.edu                entry = extern_label_longModeInterrupt;
738806Sgblack@eecs.umich.edu            }
748806Sgblack@eecs.umich.edu        } else {
758806Sgblack@eecs.umich.edu            entry = extern_label_legacyModeInterrupt;
768806Sgblack@eecs.umich.edu        }
778806Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_MICRO(1), vector);
788806Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_MICRO(7), pc);
798806Sgblack@eecs.umich.edu        if (errorCode != (uint64_t)(-1)) {
808740Sgblack@eecs.umich.edu            if (m5reg.mode == LongMode) {
818806Sgblack@eecs.umich.edu                entry = extern_label_longModeInterruptWithError;
825858Sgblack@eecs.umich.edu            } else {
838806Sgblack@eecs.umich.edu                panic("Legacy mode interrupts with error codes "
848806Sgblack@eecs.umich.edu                        "aren't implementde.\n");
855858Sgblack@eecs.umich.edu            }
868806Sgblack@eecs.umich.edu            // Software interrupts shouldn't have error codes. If one
878806Sgblack@eecs.umich.edu            // does, there would need to be microcode to set it up.
888806Sgblack@eecs.umich.edu            assert(!isSoft());
898806Sgblack@eecs.umich.edu            tc->setIntReg(INTREG_MICRO(15), errorCode);
905681Sgblack@eecs.umich.edu        }
918806Sgblack@eecs.umich.edu        pcState.upc(romMicroPC(entry));
928806Sgblack@eecs.umich.edu        pcState.nupc(romMicroPC(entry) + 1);
938806Sgblack@eecs.umich.edu        tc->pcState(pcState);
945124Sgblack@eecs.umich.edu    }
955909Sgblack@eecs.umich.edu
965909Sgblack@eecs.umich.edu    std::string
975909Sgblack@eecs.umich.edu    X86FaultBase::describe() const
985909Sgblack@eecs.umich.edu    {
995909Sgblack@eecs.umich.edu        std::stringstream ss;
1005909Sgblack@eecs.umich.edu        ccprintf(ss, "%s", mnemonic());
1015909Sgblack@eecs.umich.edu        if (errorCode != (uint64_t)(-1)) {
1025909Sgblack@eecs.umich.edu            ccprintf(ss, "(%#x)", errorCode);
1035909Sgblack@eecs.umich.edu        }
1045909Sgblack@eecs.umich.edu
1055909Sgblack@eecs.umich.edu        return ss.str();
1065909Sgblack@eecs.umich.edu    }
10711320Ssteve.reinhardt@amd.com
10810417Sandreas.hansson@arm.com    void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
1095858Sgblack@eecs.umich.edu    {
1105858Sgblack@eecs.umich.edu        X86FaultBase::invoke(tc);
1118806Sgblack@eecs.umich.edu        if (!FullSystem)
1128806Sgblack@eecs.umich.edu            return;
1138806Sgblack@eecs.umich.edu
1148806Sgblack@eecs.umich.edu        // This is the same as a fault, but it happens -after- the
1158806Sgblack@eecs.umich.edu        // instruction.
1168806Sgblack@eecs.umich.edu        PCState pc = tc->pcState();
1178806Sgblack@eecs.umich.edu        pc.uEnd();
1185858Sgblack@eecs.umich.edu    }
1195858Sgblack@eecs.umich.edu
12010417Sandreas.hansson@arm.com    void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst)
1215858Sgblack@eecs.umich.edu    {
1225858Sgblack@eecs.umich.edu        panic("Abort exception!");
1235858Sgblack@eecs.umich.edu    }
1245858Sgblack@eecs.umich.edu
1258740Sgblack@eecs.umich.edu    void
12610417Sandreas.hansson@arm.com    InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst)
1278740Sgblack@eecs.umich.edu    {
1288740Sgblack@eecs.umich.edu        if (FullSystem) {
1298740Sgblack@eecs.umich.edu            X86Fault::invoke(tc, inst);
1308740Sgblack@eecs.umich.edu        } else {
1318740Sgblack@eecs.umich.edu            panic("Unrecognized/invalid instruction executed:\n %s",
1328740Sgblack@eecs.umich.edu                    inst->machInst);
1338740Sgblack@eecs.umich.edu        }
1348740Sgblack@eecs.umich.edu    }
1358740Sgblack@eecs.umich.edu
13610417Sandreas.hansson@arm.com    void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
1375858Sgblack@eecs.umich.edu    {
1388740Sgblack@eecs.umich.edu        if (FullSystem) {
13911218Sswapnilh@cs.wisc.edu            /* Invalidate any matching TLB entries before handling the page fault */
14011218Sswapnilh@cs.wisc.edu            tc->getITBPtr()->demapPage(addr, 0);
14111218Sswapnilh@cs.wisc.edu            tc->getDTBPtr()->demapPage(addr, 0);
1428740Sgblack@eecs.umich.edu            HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
1438740Sgblack@eecs.umich.edu            X86FaultBase::invoke(tc);
1448740Sgblack@eecs.umich.edu            /*
1458740Sgblack@eecs.umich.edu             * If something bad happens while trying to enter the page fault
1468740Sgblack@eecs.umich.edu             * handler, I'm pretty sure that's a double fault and then all
1478740Sgblack@eecs.umich.edu             * bets are off. That means it should be safe to update this
1488740Sgblack@eecs.umich.edu             * state now.
1498740Sgblack@eecs.umich.edu             */
1508740Sgblack@eecs.umich.edu            if (m5reg.mode == LongMode) {
1518740Sgblack@eecs.umich.edu                tc->setMiscReg(MISCREG_CR2, addr);
1528740Sgblack@eecs.umich.edu            } else {
1538740Sgblack@eecs.umich.edu                tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
1548740Sgblack@eecs.umich.edu            }
1555858Sgblack@eecs.umich.edu        } else {
1568740Sgblack@eecs.umich.edu            PageFaultErrorCode code = errorCode;
1578740Sgblack@eecs.umich.edu            const char *modeStr = "";
1588740Sgblack@eecs.umich.edu            if (code.fetch)
1598740Sgblack@eecs.umich.edu                modeStr = "execute";
1608740Sgblack@eecs.umich.edu            else if (code.write)
1618740Sgblack@eecs.umich.edu                modeStr = "write";
1628740Sgblack@eecs.umich.edu            else
1638740Sgblack@eecs.umich.edu                modeStr = "read";
1648740Sgblack@eecs.umich.edu            panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
1655858Sgblack@eecs.umich.edu        }
1665858Sgblack@eecs.umich.edu    }
1675237Sgblack@eecs.umich.edu
1685909Sgblack@eecs.umich.edu    std::string
1695909Sgblack@eecs.umich.edu    PageFault::describe() const
1705909Sgblack@eecs.umich.edu    {
1715909Sgblack@eecs.umich.edu        std::stringstream ss;
1725909Sgblack@eecs.umich.edu        ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
1735909Sgblack@eecs.umich.edu        return ss.str();
1745909Sgblack@eecs.umich.edu    }
1755909Sgblack@eecs.umich.edu
1766048Sgblack@eecs.umich.edu    void
17710417Sandreas.hansson@arm.com    InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1786048Sgblack@eecs.umich.edu    {
1796048Sgblack@eecs.umich.edu        DPRINTF(Faults, "Init interrupt.\n");
1806048Sgblack@eecs.umich.edu        // The otherwise unmodified integer registers should be set to 0.
1816048Sgblack@eecs.umich.edu        for (int index = 0; index < NUM_INTREGS; index++) {
1826048Sgblack@eecs.umich.edu            tc->setIntReg(index, 0);
1836048Sgblack@eecs.umich.edu        }
1846048Sgblack@eecs.umich.edu
1856048Sgblack@eecs.umich.edu        CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
1866048Sgblack@eecs.umich.edu        CR0 newCR0 = 1 << 4;
1876048Sgblack@eecs.umich.edu        newCR0.cd = cr0.cd;
1886048Sgblack@eecs.umich.edu        newCR0.nw = cr0.nw;
1896048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR0, newCR0);
1906048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR2, 0);
1916048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR3, 0);
1926048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR4, 0);
1936048Sgblack@eecs.umich.edu
1946048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
1956048Sgblack@eecs.umich.edu
1966048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_EFER, 0);
1976048Sgblack@eecs.umich.edu
1986048Sgblack@eecs.umich.edu        SegAttr dataAttr = 0;
1996222Sgblack@eecs.umich.edu        dataAttr.dpl = 0;
2006222Sgblack@eecs.umich.edu        dataAttr.unusable = 0;
2016222Sgblack@eecs.umich.edu        dataAttr.defaultSize = 0;
2026222Sgblack@eecs.umich.edu        dataAttr.longMode = 0;
2036222Sgblack@eecs.umich.edu        dataAttr.avl = 0;
2046222Sgblack@eecs.umich.edu        dataAttr.granularity = 0;
2056222Sgblack@eecs.umich.edu        dataAttr.present = 1;
2066222Sgblack@eecs.umich.edu        dataAttr.type = 3;
2076048Sgblack@eecs.umich.edu        dataAttr.writable = 1;
2086048Sgblack@eecs.umich.edu        dataAttr.readable = 1;
2096048Sgblack@eecs.umich.edu        dataAttr.expandDown = 0;
2106222Sgblack@eecs.umich.edu        dataAttr.system = 1;
2116048Sgblack@eecs.umich.edu
2126048Sgblack@eecs.umich.edu        for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
2136048Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
2146048Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
2156048Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
2166048Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
2176048Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
2186048Sgblack@eecs.umich.edu        }
2196048Sgblack@eecs.umich.edu
2206048Sgblack@eecs.umich.edu        SegAttr codeAttr = 0;
2216222Sgblack@eecs.umich.edu        codeAttr.dpl = 0;
2226222Sgblack@eecs.umich.edu        codeAttr.unusable = 0;
2236222Sgblack@eecs.umich.edu        codeAttr.defaultSize = 0;
2246222Sgblack@eecs.umich.edu        codeAttr.longMode = 0;
2256222Sgblack@eecs.umich.edu        codeAttr.avl = 0;
2266222Sgblack@eecs.umich.edu        codeAttr.granularity = 0;
2276222Sgblack@eecs.umich.edu        codeAttr.present = 1;
2286222Sgblack@eecs.umich.edu        codeAttr.type = 10;
2296048Sgblack@eecs.umich.edu        codeAttr.writable = 0;
2306048Sgblack@eecs.umich.edu        codeAttr.readable = 1;
2316048Sgblack@eecs.umich.edu        codeAttr.expandDown = 0;
2326222Sgblack@eecs.umich.edu        codeAttr.system = 1;
2336048Sgblack@eecs.umich.edu
2346048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS, 0xf000);
2356048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_BASE,
2366048Sgblack@eecs.umich.edu                0x00000000ffff0000ULL);
2376048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_EFF_BASE,
2386048Sgblack@eecs.umich.edu                0x00000000ffff0000ULL);
2396048Sgblack@eecs.umich.edu        // This has the base value pre-added.
2406048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
2416048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
2426048Sgblack@eecs.umich.edu
2437720Sgblack@eecs.umich.edu        PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
2447720Sgblack@eecs.umich.edu        tc->pcState(pc);
2456048Sgblack@eecs.umich.edu
2466048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TSG_BASE, 0);
2476048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
2486048Sgblack@eecs.umich.edu
2496048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_IDTR_BASE, 0);
2506048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
2516048Sgblack@eecs.umich.edu
25210100Sandreas@sandberg.pp.se        SegAttr tslAttr = 0;
25310100Sandreas@sandberg.pp.se        tslAttr.present = 1;
25410100Sandreas@sandberg.pp.se        tslAttr.type = 2; // LDT
2556048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TSL, 0);
2566048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TSL_BASE, 0);
2576048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
25810100Sandreas@sandberg.pp.se        tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
2596048Sgblack@eecs.umich.edu
26010100Sandreas@sandberg.pp.se        SegAttr trAttr = 0;
26110100Sandreas@sandberg.pp.se        trAttr.present = 1;
26210100Sandreas@sandberg.pp.se        trAttr.type = 3; // Busy 16-bit TSS
2636048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TR, 0);
2646048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TR_BASE, 0);
2656048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
26610100Sandreas@sandberg.pp.se        tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
2676048Sgblack@eecs.umich.edu
2686048Sgblack@eecs.umich.edu        // This value should be the family/model/stepping of the processor.
2696048Sgblack@eecs.umich.edu        // (page 418). It should be consistent with the value from CPUID, but
2706048Sgblack@eecs.umich.edu        // the actual value probably doesn't matter much.
2716048Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_RDX, 0);
2726048Sgblack@eecs.umich.edu
2736048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR0, 0);
2746048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR1, 0);
2756048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR2, 0);
2766048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR3, 0);
2776048Sgblack@eecs.umich.edu
2786048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
2796048Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
2806048Sgblack@eecs.umich.edu
2819763Sandreas@sandberg.pp.se        tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
2829763Sandreas@sandberg.pp.se
2839765Sandreas@sandberg.pp.se        // Flag all elements on the x87 stack as empty.
2849765Sandreas@sandberg.pp.se        tc->setMiscReg(MISCREG_FTW, 0xFFFF);
2859765Sandreas@sandberg.pp.se
2866140Sgblack@eecs.umich.edu        // Update the handy M5 Reg.
2876140Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_M5_REG, 0);
2886048Sgblack@eecs.umich.edu        MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
2897720Sgblack@eecs.umich.edu        pc.upc(romMicroPC(entry));
2907720Sgblack@eecs.umich.edu        pc.nupc(romMicroPC(entry) + 1);
2917720Sgblack@eecs.umich.edu        tc->pcState(pc);
2926048Sgblack@eecs.umich.edu    }
2936048Sgblack@eecs.umich.edu
2946049Sgblack@eecs.umich.edu    void
29510417Sandreas.hansson@arm.com    StartupInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
2966049Sgblack@eecs.umich.edu    {
2976049Sgblack@eecs.umich.edu        DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
2986049Sgblack@eecs.umich.edu        HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
2996049Sgblack@eecs.umich.edu        if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
3006049Sgblack@eecs.umich.edu            panic("Startup IPI recived outside of real mode. "
3016140Sgblack@eecs.umich.edu                    "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
3026049Sgblack@eecs.umich.edu        }
3036049Sgblack@eecs.umich.edu
3046049Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS, vector << 8);
3056049Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
3066049Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
3076049Sgblack@eecs.umich.edu        // This has the base value pre-added.
3086049Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
3096049Sgblack@eecs.umich.edu
3107720Sgblack@eecs.umich.edu        tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
3116049Sgblack@eecs.umich.edu    }
3125124Sgblack@eecs.umich.edu} // namespace X86ISA
3135124Sgblack@eecs.umich.edu
314