emulenv.cc revision 5616:05fd71ca96db
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
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10 * use which is NOT directed to receiving any direct monetary
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12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
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17 *
18 * If you wish to use this software or functionality therein that may be
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25 *
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27 * this list of conditions and the following disclaimer.  Redistributions
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include <cassert>
59
60#include "arch/x86/emulenv.hh"
61#include "base/misc.hh"
62
63using namespace X86ISA;
64
65void EmulEnv::doModRM(const ExtMachInst & machInst)
66{
67    assert(machInst.modRM.mod != 3);
68    //Use the SIB byte for addressing if the modrm byte calls for it.
69    if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
70        scale = 1 << machInst.sib.scale;
71        index = machInst.sib.index | (machInst.rex.x << 3);
72        base = machInst.sib.base | (machInst.rex.b << 3);
73        //In this special case, we don't use a base. The displacement also
74        //changes, but that's managed by the predecoder.
75        if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
76            base = NUM_INTREGS;
77        //In -this- special case, we don't use an index.
78        if (index == INTREG_RSP)
79            index = NUM_INTREGS;
80    } else {
81        if (machInst.addrSize == 2) {
82            warn("I'm not really using 16 bit MODRM like I'm supposed to!\n");
83        } else {
84            scale = 0;
85            base = machInst.modRM.rm | (machInst.rex.b << 3);
86            if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
87                //Since we need to use a different encoding of this
88                //instruction anyway, just ignore the base in those cases
89                base = NUM_INTREGS;
90            }
91        }
92    }
93    //Figure out what segment to use. This won't be entirely accurate since
94    //the presence of a displacement is supposed to make the instruction
95    //default to the data segment.
96    if ((base != INTREG_RBP && base != INTREG_RSP) ||
97            0/*Has an immediate offset*/) {
98        seg = SEGMENT_REG_DS;
99        //Handle any segment override that might have been in the instruction
100        int segFromInst = machInst.legacy.seg;
101        if (segFromInst)
102            seg = (SegmentRegIndex)(segFromInst - 1);
103    } else {
104        seg = SEGMENT_REG_SS;
105    }
106}
107
108