cpuid.hh revision 9554:406fbcf60223
1892SN/A/*
21762SN/A * Copyright (c) 2008 The Regents of The University of Michigan
3892SN/A * All rights reserved.
4892SN/A *
5892SN/A * Redistribution and use in source and binary forms, with or without
6892SN/A * modification, are permitted provided that the following conditions are
7892SN/A * met: redistributions of source code must retain the above copyright
8892SN/A * notice, this list of conditions and the following disclaimer;
9892SN/A * redistributions in binary form must reproduce the above copyright
10892SN/A * notice, this list of conditions and the following disclaimer in the
11892SN/A * documentation and/or other materials provided with the distribution;
12892SN/A * neither the name of the copyright holders nor the names of its
13892SN/A * contributors may be used to endorse or promote products derived from
14892SN/A * this software without specific prior written permission.
15892SN/A *
16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Gabe Black
292665SN/A */
30892SN/A
31768SN/A#ifndef __ARCH_X86_CPUID_HH__
321730SN/A#define __ARCH_X86_CPUID_HH__
33768SN/A
34768SN/A#include "base/types.hh"
3511244Sandreas.sandberg@arm.com
36768SN/Aclass ThreadContext;
37768SN/A
38768SN/Anamespace X86ISA
39768SN/A{
40768SN/A    struct CpuidResult
41768SN/A    {
426658Snate@binkert.org        uint64_t rax;
438232Snate@binkert.org        uint64_t rbx;
448229Snate@binkert.org        uint64_t rcx;
4511244Sandreas.sandberg@arm.com        uint64_t rdx;
463540Sgblack@eecs.umich.edu
4711260Sandreas.sandberg@arm.com        // These are not in alphebetical order on purpose. The order reflects
482542SN/A        // how the CPUID orders the registers when it returns results.
493348SN/A        CpuidResult(uint64_t _rax, uint64_t _rbx,
50768SN/A                    uint64_t _rdx, uint64_t _rcx) :
51768SN/A            rax(_rax), rbx(_rbx), rcx(_rcx), rdx(_rdx)
52768SN/A        {}
532107SN/A
542107SN/A        CpuidResult()
55768SN/A        {}
564762Snate@binkert.org    };
5711244Sandreas.sandberg@arm.com
5811244Sandreas.sandberg@arm.com    uint64_t stringToRegister(const char *str);
5911244Sandreas.sandberg@arm.com
60768SN/A    bool doCpuid(ThreadContext * tc, uint32_t function,
61835SN/A            uint32_t index, CpuidResult &result);
62835SN/A} // namespace X86ISA
63835SN/A
64835SN/A#endif
65835SN/A