intelmp.hh revision 8737
1/* 2 * Copyright (c) 2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_BIOS_INTELMP_HH__ 41#define __ARCH_X86_BIOS_INTELMP_HH__ 42 43#include <string> 44#include <vector> 45 46#include "base/bitfield.hh" 47#include "enums/X86IntelMPAddressType.hh" 48#include "enums/X86IntelMPInterruptType.hh" 49#include "enums/X86IntelMPPolarity.hh" 50#include "enums/X86IntelMPRangeList.hh" 51#include "enums/X86IntelMPTriggerMode.hh" 52#include "sim/sim_object.hh" 53 54class PortProxy; 55 56// Config entry types 57struct X86IntelMPBaseConfigEntryParams; 58struct X86IntelMPExtConfigEntryParams; 59 60// General table structures 61struct X86IntelMPConfigTableParams; 62struct X86IntelMPFloatingPointerParams; 63 64// Base entry types 65struct X86IntelMPBusParams; 66struct X86IntelMPIOAPICParams; 67struct X86IntelMPIOIntAssignmentParams; 68struct X86IntelMPLocalIntAssignmentParams; 69struct X86IntelMPProcessorParams; 70 71// Extended entry types 72struct X86IntelMPAddrSpaceMappingParams; 73struct X86IntelMPBusHierarchyParams; 74struct X86IntelMPCompatAddrSpaceModParams; 75 76namespace X86ISA 77{ 78 79namespace IntelMP 80{ 81 82class FloatingPointer : public SimObject 83{ 84 protected: 85 typedef X86IntelMPFloatingPointerParams Params; 86 87 uint32_t tableAddr; 88 uint8_t specRev; 89 uint8_t defaultConfig; 90 bool imcrPresent; 91 92 static const char signature[]; 93 94 public: 95 96 Addr writeOut(PortProxy* proxy, Addr addr); 97 98 Addr getTableAddr() 99 { 100 return tableAddr; 101 } 102 103 void setTableAddr(Addr addr) 104 { 105 tableAddr = addr; 106 } 107 108 FloatingPointer(Params * p); 109}; 110 111class BaseConfigEntry : public SimObject 112{ 113 protected: 114 typedef X86IntelMPBaseConfigEntryParams Params; 115 116 uint8_t type; 117 118 public: 119 120 virtual Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 121 122 BaseConfigEntry(Params * p, uint8_t _type); 123}; 124 125class ExtConfigEntry : public SimObject 126{ 127 protected: 128 typedef X86IntelMPExtConfigEntryParams Params; 129 130 uint8_t type; 131 uint8_t length; 132 133 public: 134 135 virtual Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 136 137 ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length); 138}; 139 140class ConfigTable : public SimObject 141{ 142 protected: 143 typedef X86IntelMPConfigTableParams Params; 144 145 static const char signature[]; 146 147 uint8_t specRev; 148 std::string oemID; 149 std::string productID; 150 uint32_t oemTableAddr; 151 uint16_t oemTableSize; 152 uint32_t localApic; 153 154 std::vector<BaseConfigEntry *> baseEntries; 155 std::vector<ExtConfigEntry *> extEntries; 156 157 public: 158 Addr writeOut(PortProxy* proxy, Addr addr); 159 160 ConfigTable(Params * p); 161}; 162 163class Processor : public BaseConfigEntry 164{ 165 protected: 166 typedef X86IntelMPProcessorParams Params; 167 168 uint8_t localApicID; 169 uint8_t localApicVersion; 170 uint8_t cpuFlags; 171 uint32_t cpuSignature; 172 uint32_t featureFlags; 173 174 public: 175 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 176 177 Processor(Params * p); 178}; 179 180class Bus : public BaseConfigEntry 181{ 182 protected: 183 typedef X86IntelMPBusParams Params; 184 185 uint8_t busID; 186 std::string busType; 187 188 public: 189 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 190 191 Bus(Params * p); 192}; 193 194class IOAPIC : public BaseConfigEntry 195{ 196 protected: 197 typedef X86IntelMPIOAPICParams Params; 198 199 uint8_t id; 200 uint8_t version; 201 uint8_t flags; 202 uint32_t address; 203 204 public: 205 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 206 207 IOAPIC(Params * p); 208}; 209 210class IntAssignment : public BaseConfigEntry 211{ 212 protected: 213 uint8_t interruptType; 214 215 uint16_t flags; 216 217 uint8_t sourceBusID; 218 uint8_t sourceBusIRQ; 219 220 uint8_t destApicID; 221 uint8_t destApicIntIn; 222 223 public: 224 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 225 226 IntAssignment(X86IntelMPBaseConfigEntryParams * p, 227 Enums::X86IntelMPInterruptType _interruptType, 228 Enums::X86IntelMPPolarity polarity, 229 Enums::X86IntelMPTriggerMode trigger, 230 uint8_t _type, 231 uint8_t _sourceBusID, uint8_t _sourceBusIRQ, 232 uint8_t _destApicID, uint8_t _destApicIntIn) : 233 BaseConfigEntry(p, _type), 234 interruptType(_interruptType), flags(0), 235 sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ), 236 destApicID(_destApicID), destApicIntIn(_destApicIntIn) 237 { 238 replaceBits(flags, 0, 1, polarity); 239 replaceBits(flags, 2, 3, trigger); 240 } 241}; 242 243class IOIntAssignment : public IntAssignment 244{ 245 protected: 246 typedef X86IntelMPIOIntAssignmentParams Params; 247 248 public: 249 IOIntAssignment(Params * p); 250}; 251 252class LocalIntAssignment : public IntAssignment 253{ 254 protected: 255 typedef X86IntelMPLocalIntAssignmentParams Params; 256 257 public: 258 LocalIntAssignment(Params * p); 259}; 260 261class AddrSpaceMapping : public ExtConfigEntry 262{ 263 protected: 264 typedef X86IntelMPAddrSpaceMappingParams Params; 265 266 uint8_t busID; 267 uint8_t addrType; 268 uint64_t addr; 269 uint64_t addrLength; 270 271 public: 272 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 273 274 AddrSpaceMapping(Params * p); 275}; 276 277class BusHierarchy : public ExtConfigEntry 278{ 279 protected: 280 typedef X86IntelMPBusHierarchyParams Params; 281 282 uint8_t busID; 283 uint8_t info; 284 uint8_t parentBus; 285 286 public: 287 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 288 289 BusHierarchy(Params * p); 290}; 291 292class CompatAddrSpaceMod : public ExtConfigEntry 293{ 294 protected: 295 typedef X86IntelMPCompatAddrSpaceModParams Params; 296 297 uint8_t busID; 298 uint8_t mod; 299 uint32_t rangeList; 300 301 public: 302 Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); 303 304 CompatAddrSpaceMod(Params * p); 305}; 306 307} //IntelMP 308 309} //X86ISA 310 311#endif 312