intelmp.hh revision 8229
112653Sandreas.sandberg@arm.com/* 212653Sandreas.sandberg@arm.com * Copyright (c) 2008 The Hewlett-Packard Development Company 312653Sandreas.sandberg@arm.com * All rights reserved. 412653Sandreas.sandberg@arm.com * 512653Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 612653Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 712653Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 812653Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 912653Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1012653Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1112653Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1212653Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1312653Sandreas.sandberg@arm.com * 1412653Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1512653Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1612653Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 1712653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 1812653Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1912653Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2012653Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2112653Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2212653Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2312653Sandreas.sandberg@arm.com * this software without specific prior written permission. 2412653Sandreas.sandberg@arm.com * 2512653Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612653Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712653Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812653Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912653Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012653Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112653Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212653Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312653Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412653Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512653Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612653Sandreas.sandberg@arm.com * 3712653Sandreas.sandberg@arm.com * Authors: Gabe Black 3812653Sandreas.sandberg@arm.com */ 3912653Sandreas.sandberg@arm.com 4012653Sandreas.sandberg@arm.com#ifndef __ARCH_X86_BIOS_INTELMP_HH__ 4112653Sandreas.sandberg@arm.com#define __ARCH_X86_BIOS_INTELMP_HH__ 4212653Sandreas.sandberg@arm.com 4312653Sandreas.sandberg@arm.com#include <string> 4412653Sandreas.sandberg@arm.com#include <vector> 4512653Sandreas.sandberg@arm.com 4612653Sandreas.sandberg@arm.com#include "base/bitfield.hh" 4712653Sandreas.sandberg@arm.com#include "enums/X86IntelMPAddressType.hh" 4812653Sandreas.sandberg@arm.com#include "enums/X86IntelMPInterruptType.hh" 4912653Sandreas.sandberg@arm.com#include "enums/X86IntelMPPolarity.hh" 5012653Sandreas.sandberg@arm.com#include "enums/X86IntelMPRangeList.hh" 5112653Sandreas.sandberg@arm.com#include "enums/X86IntelMPTriggerMode.hh" 5212653Sandreas.sandberg@arm.com#include "sim/sim_object.hh" 5312653Sandreas.sandberg@arm.com 5412653Sandreas.sandberg@arm.comclass FunctionalPort; 5512653Sandreas.sandberg@arm.com 5612653Sandreas.sandberg@arm.com// Config entry types 5712653Sandreas.sandberg@arm.comclass X86IntelMPBaseConfigEntryParams; 5812653Sandreas.sandberg@arm.comclass X86IntelMPExtConfigEntryParams; 5912653Sandreas.sandberg@arm.com 6012653Sandreas.sandberg@arm.com// General table structures 6112653Sandreas.sandberg@arm.comclass X86IntelMPConfigTableParams; 6212653Sandreas.sandberg@arm.comclass X86IntelMPFloatingPointerParams; 6312653Sandreas.sandberg@arm.com 6412653Sandreas.sandberg@arm.com// Base entry types 6512653Sandreas.sandberg@arm.comclass X86IntelMPBusParams; 6612653Sandreas.sandberg@arm.comclass X86IntelMPIOAPICParams; 6712653Sandreas.sandberg@arm.comclass X86IntelMPIOIntAssignmentParams; 6812653Sandreas.sandberg@arm.comclass X86IntelMPLocalIntAssignmentParams; 6912653Sandreas.sandberg@arm.comclass X86IntelMPProcessorParams; 7012653Sandreas.sandberg@arm.com 7112653Sandreas.sandberg@arm.com// Extended entry types 7212653Sandreas.sandberg@arm.comclass X86IntelMPAddrSpaceMappingParams; 7312653Sandreas.sandberg@arm.comclass X86IntelMPBusHierarchyParams; 7412653Sandreas.sandberg@arm.comclass X86IntelMPCompatAddrSpaceModParams; 7512653Sandreas.sandberg@arm.com 7612653Sandreas.sandberg@arm.comnamespace X86ISA 7712653Sandreas.sandberg@arm.com{ 7812653Sandreas.sandberg@arm.com 7912653Sandreas.sandberg@arm.comnamespace IntelMP 8012653Sandreas.sandberg@arm.com{ 8112653Sandreas.sandberg@arm.com 8212653Sandreas.sandberg@arm.comclass FloatingPointer : public SimObject 8312653Sandreas.sandberg@arm.com{ 8412653Sandreas.sandberg@arm.com protected: 8512653Sandreas.sandberg@arm.com typedef X86IntelMPFloatingPointerParams Params; 8612653Sandreas.sandberg@arm.com 8712653Sandreas.sandberg@arm.com uint32_t tableAddr; 8812653Sandreas.sandberg@arm.com uint8_t specRev; 8912653Sandreas.sandberg@arm.com uint8_t defaultConfig; 9012653Sandreas.sandberg@arm.com bool imcrPresent; 9112653Sandreas.sandberg@arm.com 9212653Sandreas.sandberg@arm.com static const char signature[]; 9312653Sandreas.sandberg@arm.com 9412653Sandreas.sandberg@arm.com public: 9512653Sandreas.sandberg@arm.com 9612653Sandreas.sandberg@arm.com Addr writeOut(FunctionalPort * port, Addr addr); 9712653Sandreas.sandberg@arm.com 9812653Sandreas.sandberg@arm.com Addr getTableAddr() 9912653Sandreas.sandberg@arm.com { 10012653Sandreas.sandberg@arm.com return tableAddr; 10112653Sandreas.sandberg@arm.com } 10212653Sandreas.sandberg@arm.com 10312653Sandreas.sandberg@arm.com void setTableAddr(Addr addr) 10412653Sandreas.sandberg@arm.com { 10512653Sandreas.sandberg@arm.com tableAddr = addr; 10612653Sandreas.sandberg@arm.com } 10712653Sandreas.sandberg@arm.com 10812653Sandreas.sandberg@arm.com FloatingPointer(Params * p); 10912653Sandreas.sandberg@arm.com}; 11012653Sandreas.sandberg@arm.com 11112653Sandreas.sandberg@arm.comclass BaseConfigEntry : public SimObject 11212653Sandreas.sandberg@arm.com{ 11312653Sandreas.sandberg@arm.com protected: 11412653Sandreas.sandberg@arm.com typedef X86IntelMPBaseConfigEntryParams Params; 11512653Sandreas.sandberg@arm.com 11612653Sandreas.sandberg@arm.com uint8_t type; 11712653Sandreas.sandberg@arm.com 11812653Sandreas.sandberg@arm.com public: 11912653Sandreas.sandberg@arm.com 12012653Sandreas.sandberg@arm.com virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 12112653Sandreas.sandberg@arm.com 12212653Sandreas.sandberg@arm.com BaseConfigEntry(Params * p, uint8_t _type); 12312653Sandreas.sandberg@arm.com}; 12412653Sandreas.sandberg@arm.com 12512653Sandreas.sandberg@arm.comclass ExtConfigEntry : public SimObject 12612653Sandreas.sandberg@arm.com{ 12712653Sandreas.sandberg@arm.com protected: 12812653Sandreas.sandberg@arm.com typedef X86IntelMPExtConfigEntryParams Params; 12912653Sandreas.sandberg@arm.com 13012653Sandreas.sandberg@arm.com uint8_t type; 13112653Sandreas.sandberg@arm.com uint8_t length; 13212653Sandreas.sandberg@arm.com 13312653Sandreas.sandberg@arm.com public: 13412653Sandreas.sandberg@arm.com 135 virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 136 137 ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length); 138}; 139 140class ConfigTable : public SimObject 141{ 142 protected: 143 typedef X86IntelMPConfigTableParams Params; 144 145 static const char signature[]; 146 147 uint8_t specRev; 148 std::string oemID; 149 std::string productID; 150 uint32_t oemTableAddr; 151 uint16_t oemTableSize; 152 uint32_t localApic; 153 154 std::vector<BaseConfigEntry *> baseEntries; 155 std::vector<ExtConfigEntry *> extEntries; 156 157 public: 158 Addr writeOut(FunctionalPort * port, Addr addr); 159 160 ConfigTable(Params * p); 161}; 162 163class Processor : public BaseConfigEntry 164{ 165 protected: 166 typedef X86IntelMPProcessorParams Params; 167 168 uint8_t localApicID; 169 uint8_t localApicVersion; 170 uint8_t cpuFlags; 171 uint32_t cpuSignature; 172 uint32_t featureFlags; 173 174 public: 175 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 176 177 Processor(Params * p); 178}; 179 180class Bus : public BaseConfigEntry 181{ 182 protected: 183 typedef X86IntelMPBusParams Params; 184 185 uint8_t busID; 186 std::string busType; 187 188 public: 189 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 190 191 Bus(Params * p); 192}; 193 194class IOAPIC : public BaseConfigEntry 195{ 196 protected: 197 typedef X86IntelMPIOAPICParams Params; 198 199 uint8_t id; 200 uint8_t version; 201 uint8_t flags; 202 uint32_t address; 203 204 public: 205 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 206 207 IOAPIC(Params * p); 208}; 209 210class IntAssignment : public BaseConfigEntry 211{ 212 protected: 213 uint8_t interruptType; 214 215 uint16_t flags; 216 217 uint8_t sourceBusID; 218 uint8_t sourceBusIRQ; 219 220 uint8_t destApicID; 221 uint8_t destApicIntIn; 222 223 public: 224 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 225 226 IntAssignment(X86IntelMPBaseConfigEntryParams * p, 227 Enums::X86IntelMPInterruptType _interruptType, 228 Enums::X86IntelMPPolarity polarity, 229 Enums::X86IntelMPTriggerMode trigger, 230 uint8_t _type, 231 uint8_t _sourceBusID, uint8_t _sourceBusIRQ, 232 uint8_t _destApicID, uint8_t _destApicIntIn) : 233 BaseConfigEntry(p, _type), 234 interruptType(_interruptType), flags(0), 235 sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ), 236 destApicID(_destApicID), destApicIntIn(_destApicIntIn) 237 { 238 replaceBits(flags, 0, 1, polarity); 239 replaceBits(flags, 2, 3, trigger); 240 } 241}; 242 243class IOIntAssignment : public IntAssignment 244{ 245 protected: 246 typedef X86IntelMPIOIntAssignmentParams Params; 247 248 public: 249 IOIntAssignment(Params * p); 250}; 251 252class LocalIntAssignment : public IntAssignment 253{ 254 protected: 255 typedef X86IntelMPLocalIntAssignmentParams Params; 256 257 public: 258 LocalIntAssignment(Params * p); 259}; 260 261class AddrSpaceMapping : public ExtConfigEntry 262{ 263 protected: 264 typedef X86IntelMPAddrSpaceMappingParams Params; 265 266 uint8_t busID; 267 uint8_t addrType; 268 uint64_t addr; 269 uint64_t addrLength; 270 271 public: 272 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 273 274 AddrSpaceMapping(Params * p); 275}; 276 277class BusHierarchy : public ExtConfigEntry 278{ 279 protected: 280 typedef X86IntelMPBusHierarchyParams Params; 281 282 uint8_t busID; 283 uint8_t info; 284 uint8_t parentBus; 285 286 public: 287 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 288 289 BusHierarchy(Params * p); 290}; 291 292class CompatAddrSpaceMod : public ExtConfigEntry 293{ 294 protected: 295 typedef X86IntelMPCompatAddrSpaceModParams Params; 296 297 uint8_t busID; 298 uint8_t mod; 299 uint32_t rangeList; 300 301 public: 302 Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); 303 304 CompatAddrSpaceMod(Params * p); 305}; 306 307} //IntelMP 308 309} //X86ISA 310 311#endif 312