intelmp.hh revision 5625
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_BIOS_INTELMP_HH__
59#define __ARCH_X86_BIOS_INTELMP_HH__
60
61#include <string>
62#include <vector>
63
64#include "base/bitfield.hh"
65#include "sim/sim_object.hh"
66
67#include "enums/X86IntelMPAddressType.hh"
68#include "enums/X86IntelMPInterruptType.hh"
69#include "enums/X86IntelMPPolarity.hh"
70#include "enums/X86IntelMPRangeList.hh"
71#include "enums/X86IntelMPTriggerMode.hh"
72
73class FunctionalPort;
74
75// Config entry types
76class X86IntelMPBaseConfigEntryParams;
77class X86IntelMPExtConfigEntryParams;
78
79// General table structures
80class X86IntelMPConfigTableParams;
81class X86IntelMPFloatingPointerParams;
82
83// Base entry types
84class X86IntelMPBusParams;
85class X86IntelMPIOAPICParams;
86class X86IntelMPIOIntAssignmentParams;
87class X86IntelMPLocalIntAssignmentParams;
88class X86IntelMPProcessorParams;
89
90// Extended entry types
91class X86IntelMPAddrSpaceMappingParams;
92class X86IntelMPBusHierarchyParams;
93class X86IntelMPCompatAddrSpaceModParams;
94
95namespace X86ISA
96{
97
98namespace IntelMP
99{
100
101class FloatingPointer : public SimObject
102{
103  protected:
104    typedef X86IntelMPFloatingPointerParams Params;
105
106    uint32_t tableAddr;
107    uint8_t specRev;
108    uint8_t defaultConfig;
109    bool imcrPresent;
110
111    static const char signature[];
112
113  public:
114
115    Addr writeOut(FunctionalPort * port, Addr addr);
116
117    Addr getTableAddr()
118    {
119        return tableAddr;
120    }
121
122    void setTableAddr(Addr addr)
123    {
124        tableAddr = addr;
125    }
126
127    FloatingPointer(Params * p);
128};
129
130class BaseConfigEntry : public SimObject
131{
132  protected:
133    typedef X86IntelMPBaseConfigEntryParams Params;
134
135    uint8_t type;
136
137  public:
138
139    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
140
141    BaseConfigEntry(Params * p, uint8_t _type);
142};
143
144class ExtConfigEntry : public SimObject
145{
146  protected:
147    typedef X86IntelMPExtConfigEntryParams Params;
148
149    uint8_t type;
150    uint8_t length;
151
152  public:
153
154    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
155
156    ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
157};
158
159class ConfigTable : public SimObject
160{
161  protected:
162    typedef X86IntelMPConfigTableParams Params;
163
164    static const char signature[];
165
166    uint8_t specRev;
167    std::string oemID;
168    std::string productID;
169    uint32_t oemTableAddr;
170    uint16_t oemTableSize;
171    uint32_t localApic;
172
173    std::vector<BaseConfigEntry *> baseEntries;
174    std::vector<ExtConfigEntry *> extEntries;
175
176  public:
177    Addr writeOut(FunctionalPort * port, Addr addr);
178
179    ConfigTable(Params * p);
180};
181
182class Processor : public BaseConfigEntry
183{
184  protected:
185    typedef X86IntelMPProcessorParams Params;
186
187    uint8_t localApicID;
188    uint8_t localApicVersion;
189    uint8_t cpuFlags;
190    uint32_t cpuSignature;
191    uint32_t featureFlags;
192
193  public:
194    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
195
196    Processor(Params * p);
197};
198
199class Bus : public BaseConfigEntry
200{
201  protected:
202    typedef X86IntelMPBusParams Params;
203
204    uint8_t busID;
205    std::string busType;
206
207  public:
208    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
209
210    Bus(Params * p);
211};
212
213class IOAPIC : public BaseConfigEntry
214{
215  protected:
216    typedef X86IntelMPIOAPICParams Params;
217
218    uint8_t id;
219    uint8_t version;
220    uint8_t flags;
221    uint32_t address;
222
223  public:
224    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
225
226    IOAPIC(Params * p);
227};
228
229class IntAssignment : public BaseConfigEntry
230{
231  protected:
232    uint8_t interruptType;
233
234    uint16_t flags;
235
236    uint8_t sourceBusID;
237    uint8_t sourceBusIRQ;
238
239    uint8_t destApicID;
240    uint8_t destApicIntIn;
241
242  public:
243    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
244
245    IntAssignment(X86IntelMPBaseConfigEntryParams * p,
246            Enums::X86IntelMPInterruptType _interruptType,
247            Enums::X86IntelMPPolarity polarity,
248            Enums::X86IntelMPTriggerMode trigger,
249            uint8_t _type,
250            uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
251            uint8_t _destApicID, uint8_t _destApicIntIn) :
252        BaseConfigEntry(p, _type),
253        interruptType(_interruptType), flags(0),
254        sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
255        destApicID(_destApicID), destApicIntIn(_destApicIntIn)
256    {
257        replaceBits(flags, 0, 1, polarity);
258        replaceBits(flags, 2, 3, trigger);
259    }
260};
261
262class IOIntAssignment : public IntAssignment
263{
264  protected:
265    typedef X86IntelMPIOIntAssignmentParams Params;
266
267  public:
268    IOIntAssignment(Params * p);
269};
270
271class LocalIntAssignment : public IntAssignment
272{
273  protected:
274    typedef X86IntelMPLocalIntAssignmentParams Params;
275
276  public:
277    LocalIntAssignment(Params * p);
278};
279
280class AddrSpaceMapping : public ExtConfigEntry
281{
282  protected:
283    typedef X86IntelMPAddrSpaceMappingParams Params;
284
285    uint8_t busID;
286    uint8_t addrType;
287    uint64_t addr;
288    uint64_t addrLength;
289
290  public:
291    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
292
293    AddrSpaceMapping(Params * p);
294};
295
296class BusHierarchy : public ExtConfigEntry
297{
298  protected:
299    typedef X86IntelMPBusHierarchyParams Params;
300
301    uint8_t busID;
302    uint8_t info;
303    uint8_t parentBus;
304
305  public:
306    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
307
308    BusHierarchy(Params * p);
309};
310
311class CompatAddrSpaceMod : public ExtConfigEntry
312{
313  protected:
314    typedef X86IntelMPCompatAddrSpaceModParams Params;
315
316    uint8_t busID;
317    uint8_t mod;
318    uint32_t rangeList;
319
320  public:
321    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
322
323    CompatAddrSpaceMod(Params * p);
324};
325
326} //IntelMP
327
328} //X86ISA
329
330#endif
331