IntelMP.py revision 5838:47ada83a8958
1# Copyright (c) 2008 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any 9# use which is NOT directed to receiving any direct monetary 10# compensation for, or commercial advantage from such use. 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Neither the name of 30# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31# contributors may be used to endorse or promote products derived from 32# this software without specific prior written permission. No right of 33# sublicense is granted herewith. Derivatives of the software and 34# output created using the software may be prepared, but only for 35# Non-Commercial Uses. Derivatives of the software may be shared with 36# others provided: (i) the others agree to abide by the list of 37# conditions herein which includes the Non-Commercial Use restrictions; 38# and (ii) such Derivatives of the software include the above copyright 39# notice to acknowledge the contribution from this software where 40# applicable, this list of conditions and the disclaimer below. 41# 42# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 56from m5.params import * 57from m5.SimObject import SimObject 58 59class X86IntelMPFloatingPointer(SimObject): 60 type = 'X86IntelMPFloatingPointer' 61 cxx_class = 'X86ISA::IntelMP::FloatingPointer' 62 63 # The minor revision of the spec to support. The major version is assumed 64 # to be 1 in accordance with the spec. 65 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported') 66 # If no default configuration is used, set this to 0. 67 default_config = Param.UInt8(0, 'which default configuration to use') 68 imcr_present = Param.Bool(True, 69 'whether the IMCR register is present in the APIC') 70 71class X86IntelMPConfigTable(SimObject): 72 type = 'X86IntelMPConfigTable' 73 cxx_class = 'X86ISA::IntelMP::ConfigTable' 74 75 spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported') 76 oem_id = Param.String("", 'system manufacturer') 77 product_id = Param.String("", 'product family') 78 oem_table_addr = Param.UInt32(0, 79 'pointer to the optional oem configuration table') 80 oem_table_size = Param.UInt16(0, 'size of the oem configuration table') 81 local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC') 82 83 base_entries = VectorParam.X86IntelMPBaseConfigEntry([], 84 'base configuration table entries') 85 86 ext_entries = VectorParam.X86IntelMPExtConfigEntry([], 87 'extended configuration table entries') 88 89 def add_entry(self, entry): 90 if isinstance(entry, X86IntelMPBaseConfigEntry): 91 self.base_entries.append(entry) 92 elif isinstance(entry, X86IntelMPExtConfigEntry): 93 self.ext_entries.append(entry) 94 else: 95 panic("Don't know what type of Intel MP entry %s is." \ 96 % entry.__class__.__name__) 97 98class X86IntelMPBaseConfigEntry(SimObject): 99 type = 'X86IntelMPBaseConfigEntry' 100 cxx_class = 'X86ISA::IntelMP::BaseConfigEntry' 101 abstract = True 102 103class X86IntelMPExtConfigEntry(SimObject): 104 type = 'X86IntelMPExtConfigEntry' 105 cxx_class = 'X86ISA::IntelMP::ExtConfigEntry' 106 abstract = True 107 108class X86IntelMPProcessor(X86IntelMPBaseConfigEntry): 109 type = 'X86IntelMPProcessor' 110 cxx_class = 'X86ISA::IntelMP::Processor' 111 112 local_apic_id = Param.UInt8(0, 'local APIC id') 113 local_apic_version = Param.UInt8(0, 114 'bits 0-7 of the local APIC version register') 115 enable = Param.Bool(True, 'if this processor is usable') 116 bootstrap = Param.Bool(False, 'if this is the bootstrap processor') 117 118 stepping = Param.UInt8(0, 'Processor stepping') 119 model = Param.UInt8(0, 'Processor model') 120 family = Param.UInt8(0, 'Processor family') 121 122 feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction') 123 124class X86IntelMPBus(X86IntelMPBaseConfigEntry): 125 type = 'X86IntelMPBus' 126 cxx_class = 'X86ISA::IntelMP::Bus' 127 128 bus_id = Param.UInt8(0, 'bus id assigned by the bios') 129 bus_type = Param.String("", 'string that identify the bus type') 130 # Legal values for bus_type are: 131 # 132 # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII", 133 # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME", 134 # "XPRESS" 135 136class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry): 137 type = 'X86IntelMPIOAPIC' 138 cxx_class = 'X86ISA::IntelMP::IOAPIC' 139 140 id = Param.UInt8(0, 'id of this APIC') 141 version = Param.UInt8(0, 'bits 0-7 of the version register') 142 143 enable = Param.Bool(True, 'if this APIC is usable') 144 145 address = Param.UInt32(0xfec00000, 'address of this APIC') 146 147class X86IntelMPInterruptType(Enum): 148 map = {'INT' : 0, 149 'NMI' : 1, 150 'SMI' : 2, 151 'ExtInt' : 3 152 } 153 154class X86IntelMPPolarity(Enum): 155 map = {'ConformPolarity' : 0, 156 'ActiveHigh' : 1, 157 'ActiveLow' : 3 158 } 159 160class X86IntelMPTriggerMode(Enum): 161 map = {'ConformTrigger' : 0, 162 'EdgeTrigger' : 1, 163 'LevelTrigger' : 3 164 } 165 166class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry): 167 type = 'X86IntelMPIOIntAssignment' 168 cxx_class = 'X86ISA::IntelMP::IOIntAssignment' 169 170 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') 171 172 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity') 173 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode') 174 175 source_bus_id = Param.UInt8(0, 176 'id of the bus from which the interrupt signal comes') 177 source_bus_irq = Param.UInt8(0, 178 'which interrupt signal from the source bus') 179 180 dest_io_apic_id = Param.UInt8(0, 181 'id of the IO APIC the interrupt is going to') 182 dest_io_apic_intin = Param.UInt8(0, 183 'the INTIN pin on the IO APIC the interrupt is connected to') 184 185class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry): 186 type = 'X86IntelMPLocalIntAssignment' 187 cxx_class = 'X86ISA::IntelMP::LocalIntAssignment' 188 189 interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') 190 191 polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity') 192 trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode') 193 194 source_bus_id = Param.UInt8(0, 195 'id of the bus from which the interrupt signal comes') 196 source_bus_irq = Param.UInt8(0, 197 'which interrupt signal from the source bus') 198 199 dest_local_apic_id = Param.UInt8(0, 200 'id of the local APIC the interrupt is going to') 201 dest_local_apic_intin = Param.UInt8(0, 202 'the INTIN pin on the local APIC the interrupt is connected to') 203 204class X86IntelMPAddressType(Enum): 205 map = {"IOAddress" : 0, 206 "MemoryAddress" : 1, 207 "PrefetchAddress" : 2 208 } 209 210class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry): 211 type = 'X86IntelMPAddrSpaceMapping' 212 cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping' 213 214 bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to') 215 address_type = Param.X86IntelMPAddressType('IOAddress', 216 'address type used to access bus') 217 address = Param.Addr(0, 'starting address of the mapping') 218 length = Param.UInt64(0, 'length of mapping in bytes') 219 220class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry): 221 type = 'X86IntelMPBusHierarchy' 222 cxx_class = 'X86ISA::IntelMP::BusHierarchy' 223 224 bus_id = Param.UInt8(0, 'id of the bus being described') 225 subtractive_decode = Param.Bool(False, 226 'whether this bus contains all addresses not used by its children') 227 parent_bus = Param.UInt8(0, 'bus id of this busses parent') 228 229class X86IntelMPRangeList(Enum): 230 map = {"ISACompatible" : 0, 231 "VGACompatible" : 1 232 } 233 234class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry): 235 type = 'X86IntelMPCompatAddrSpaceMod' 236 cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod' 237 238 bus_id = Param.UInt8(0, 'id of the bus being described') 239 add = Param.Bool(False, 240 'if the range should be added to the original mapping') 241 range_list = Param.X86IntelMPRangeList('ISACompatible', 242 'which predefined range of addresses to use') 243