X86TLB.py revision 9818 
1# Copyright (c) 2007 The Hewlett-Packard Development Company
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36# Authors: Gabe Black
37
38from m5.params import *
39from m5.proxy import *
40
41from BaseTLB import BaseTLB
42from MemObject import MemObject
43
44class X86PagetableWalker(MemObject):
45    type = 'X86PagetableWalker'
46    cxx_class = 'X86ISA::Walker'
47    cxx_header = 'arch/x86/pagetable_walker.hh'
48    port = MasterPort("Port for the hardware table walker")
49    system = Param.System(Parent.any, "system object")
50    num_squash_per_cycle = Param.Unsigned(4,
51            "Number of outstanding walks that can be squashed per cycle")
52
53class X86TLB(BaseTLB):
54    type = 'X86TLB'
55    cxx_class = 'X86ISA::TLB'
56    cxx_header = 'arch/x86/tlb.hh'
57    size = Param.Unsigned(64, "TLB size")
58    walker = Param.X86PagetableWalker(\
59            X86PagetableWalker(), "page table walker")
60