xref: /gem5/src/arch/x86/X86TLB.py

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# Authors: Gabe Black

from MemObject import MemObject
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5 import build_env

if build_env['FULL_SYSTEM']:
    class X86PagetableWalker(MemObject):
        type = 'X86PagetableWalker'
        cxx_namespace = 'X86ISA'
        cxx_class = 'Walker'
        port = Port("Port for the hardware table walker")
        system = Param.System(Parent.any, "system object")

class X86TLB(SimObject):
    type = 'X86TLB'
    cxx_namespace = 'X86ISA'
    cxx_class = 'TLB'
    abstract = True
    size = Param.Int("TLB size")
    if build_env['FULL_SYSTEM']:
        walker = Param.X86PagetableWalker(\
                X86PagetableWalker(), "page table walker")

class X86DTB(X86TLB):
    type = 'X86DTB'
    cxx_namespace = 'X86ISA'
    cxx_class = 'DTB'

    size = 64

class X86ITB(X86TLB):
    type = 'X86ITB'
    cxx_namespace = 'X86ISA'
    cxx_class = 'ITB'

    size = 64