utility.hh revision 4181:6edaeff44647 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/misc.hh"
38#include "base/bitfield.hh"
39#include "cpu/thread_context.hh"
40
41namespace SparcISA
42{
43
44    static inline bool
45    inUserMode(ThreadContext *tc)
46    {
47        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
48                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
49    }
50
51    enum PredecodeResult {
52        MoreBytes = 1,
53        ExtMIReady = 2
54    };
55
56    inline unsigned int
57    predecode(ExtMachInst &emi, Addr currPC, MachInst inst,
58            ThreadContext * xc) {
59        emi = inst;
60        //The I bit, bit 13, is used to figure out where the ASI
61        //should come from. Use that in the ExtMachInst. This is
62        //slightly redundant, but it removes the need to put a condition
63        //into all the execute functions
64        if(inst & (1 << 13))
65            emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
66                    << (sizeof(MachInst) * 8));
67        else
68            emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
69                    << (sizeof(MachInst) * 8));
70        return MoreBytes | ExtMIReady;
71    }
72
73    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
74        panic("register classification not implemented");
75        return false;
76    }
77
78    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
79        panic("register classification not implemented");
80        return false;
81    }
82
83    inline bool isCallerSaveFloatRegister(unsigned int reg) {
84        panic("register classification not implemented");
85        return false;
86    }
87
88    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
89        panic("register classification not implemented");
90        return false;
91    }
92
93    // Instruction address compression hooks
94    inline Addr realPCToFetchPC(const Addr &addr)
95    {
96        return addr;
97    }
98
99    inline Addr fetchPCToRealPC(const Addr &addr)
100    {
101        return addr;
102    }
103
104    // the size of "fetched" instructions (not necessarily the size
105    // of real instructions for PISA)
106    inline size_t fetchInstSize()
107    {
108        return sizeof(MachInst);
109    }
110
111    /**
112     * Function to insure ISA semantics about 0 registers.
113     * @param tc The thread context.
114     */
115    template <class TC>
116    void zeroRegisters(TC *tc);
117
118    inline void initCPU(ThreadContext *tc, int cpuId)
119    {
120        static Fault por = new PowerOnReset();
121        por->invoke(tc);
122    }
123
124} // namespace SparcISA
125
126#endif
127