utility.hh revision 4172:141705d83494 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/misc.hh"
38#include "base/bitfield.hh"
39#include "cpu/thread_context.hh"
40
41namespace SparcISA
42{
43
44    static inline bool
45    inUserMode(ThreadContext *tc)
46    {
47        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
48                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
49    }
50
51    inline ExtMachInst
52    makeExtMI(MachInst inst, ThreadContext * xc) {
53        ExtMachInst emi = (MachInst) inst;
54        //The I bit, bit 13, is used to figure out where the ASI
55        //should come from. Use that in the ExtMachInst. This is
56        //slightly redundant, but it removes the need to put a condition
57        //into all the execute functions
58        if(inst & (1 << 13))
59            emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
60                    << (sizeof(MachInst) * 8));
61        else
62            emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
63                    << (sizeof(MachInst) * 8));
64        return emi;
65    }
66
67    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
68        panic("register classification not implemented");
69        return false;
70    }
71
72    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
73        panic("register classification not implemented");
74        return false;
75    }
76
77    inline bool isCallerSaveFloatRegister(unsigned int reg) {
78        panic("register classification not implemented");
79        return false;
80    }
81
82    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
83        panic("register classification not implemented");
84        return false;
85    }
86
87    // Instruction address compression hooks
88    inline Addr realPCToFetchPC(const Addr &addr)
89    {
90        return addr;
91    }
92
93    inline Addr fetchPCToRealPC(const Addr &addr)
94    {
95        return addr;
96    }
97
98    // the size of "fetched" instructions (not necessarily the size
99    // of real instructions for PISA)
100    inline size_t fetchInstSize()
101    {
102        return sizeof(MachInst);
103    }
104
105    /**
106     * Function to insure ISA semantics about 0 registers.
107     * @param tc The thread context.
108     */
109    template <class TC>
110    void zeroRegisters(TC *tc);
111
112    inline void initCPU(ThreadContext *tc, int cpuId)
113    {
114        static Fault por = new PowerOnReset();
115        por->invoke(tc);
116    }
117
118} // namespace SparcISA
119
120#endif
121