utility.hh revision 3577:605c370622b1 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "base/misc.hh"
37#include "base/bitfield.hh"
38#include "cpu/thread_context.hh"
39
40namespace SparcISA
41{
42
43    static inline bool
44    inUserMode(ThreadContext *tc)
45    {
46        return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) ||
47                tc->readMiscReg(MISCREG_HPSTATE & (1 << 2)));
48    }
49
50    inline ExtMachInst
51    makeExtMI(MachInst inst, ThreadContext * xc) {
52        ExtMachInst emi = (unsigned MachInst) inst;
53        //The I bit, bit 13, is used to figure out where the ASI
54        //should come from. Use that in the ExtMachInst. This is
55        //slightly redundant, but it removes the need to put a condition
56        //into all the execute functions
57        if(inst & (1 << 13))
58            emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
59                    << (sizeof(MachInst) * 8));
60        else
61            emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
62                    << (sizeof(MachInst) * 8));
63        return emi;
64    }
65
66    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
67        panic("register classification not implemented");
68        return false;
69    }
70
71    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
72        panic("register classification not implemented");
73        return false;
74    }
75
76    inline bool isCallerSaveFloatRegister(unsigned int reg) {
77        panic("register classification not implemented");
78        return false;
79    }
80
81    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
82        panic("register classification not implemented");
83        return false;
84    }
85
86    // Instruction address compression hooks
87    inline Addr realPCToFetchPC(const Addr &addr)
88    {
89        return addr;
90    }
91
92    inline Addr fetchPCToRealPC(const Addr &addr)
93    {
94        return addr;
95    }
96
97    // the size of "fetched" instructions (not necessarily the size
98    // of real instructions for PISA)
99    inline size_t fetchInstSize()
100    {
101        return sizeof(MachInst);
102    }
103
104    /**
105     * Function to insure ISA semantics about 0 registers.
106     * @param tc The thread context.
107     */
108    template <class TC>
109    void zeroRegisters(TC *tc);
110
111    inline void initCPU(ThreadContext *tc, int cpuId)
112    {
113        static Fault por = new PowerOnReset();
114        por->invoke(tc);
115    }
116
117} // namespace SparcISA
118
119#endif
120