utility.hh revision 2665:a124942bacb8 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/isa_traits.hh"
35#include "base/misc.hh"
36
37namespace SparcISA
38{
39    inline ExtMachInst
40    makeExtMI(MachInst inst, const Addr &pc) {
41        return ExtMachInst(inst);
42    }
43
44    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
45        panic("register classification not implemented");
46        return false;
47    }
48
49    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
50        panic("register classification not implemented");
51        return false;
52    }
53
54    inline bool isCallerSaveFloatRegister(unsigned int reg) {
55        panic("register classification not implemented");
56        return false;
57    }
58
59    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
60        panic("register classification not implemented");
61        return false;
62    }
63
64    // Instruction address compression hooks
65    inline Addr realPCToFetchPC(const Addr &addr)
66    {
67        return addr;
68    }
69
70    inline Addr fetchPCToRealPC(const Addr &addr)
71    {
72        return addr;
73    }
74
75    // the size of "fetched" instructions (not necessarily the size
76    // of real instructions for PISA)
77    inline size_t fetchInstSize()
78    {
79        return sizeof(MachInst);
80    }
81
82    /**
83     * Function to insure ISA semantics about 0 registers.
84     * @param xc The execution context.
85     */
86    template <class XC>
87    void zeroRegisters(XC *xc);
88
89} // namespace SparcISA
90
91#endif
92