utility.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_SPARC_UTILITY_HH__
30#define __ARCH_SPARC_UTILITY_HH__
31
32#include "arch/sparc/isa_traits.hh"
33#include "base/misc.hh"
34
35namespace SparcISA
36{
37    inline ExtMachInst
38    makeExtMI(MachInst inst, const Addr &pc) {
39        return ExtMachInst(inst);
40    }
41
42    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
43        panic("register classification not implemented");
44        return false;
45    }
46
47    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
48        panic("register classification not implemented");
49        return false;
50    }
51
52    inline bool isCallerSaveFloatRegister(unsigned int reg) {
53        panic("register classification not implemented");
54        return false;
55    }
56
57    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
58        panic("register classification not implemented");
59        return false;
60    }
61
62    // Instruction address compression hooks
63    inline Addr realPCToFetchPC(const Addr &addr)
64    {
65        return addr;
66    }
67
68    inline Addr fetchPCToRealPC(const Addr &addr)
69    {
70        return addr;
71    }
72
73    // the size of "fetched" instructions (not necessarily the size
74    // of real instructions for PISA)
75    inline size_t fetchInstSize()
76    {
77        return sizeof(MachInst);
78    }
79
80    /**
81     * Function to insure ISA semantics about 0 registers.
82     * @param xc The execution context.
83     */
84    template <class XC>
85    void zeroRegisters(XC *xc);
86
87} // namespace SparcISA
88
89#endif
90