utility.cc revision 8706:b1838faf3bcc 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#include "arch/sparc/faults.hh"
33#include "arch/sparc/utility.hh"
34#if FULL_SYSTEM
35#include "arch/sparc/vtophys.hh"
36#include "mem/fs_translating_port_proxy.hh"
37#endif
38
39namespace SparcISA {
40
41
42// The caller uses %o0-%05 for the first 6 arguments even if their floating
43// point. Double precision floating point values take two registers/args.
44// Quads, structs, and unions are passed as pointers. All arguments beyond
45// the sixth are passed on the stack past the 16 word window save area,
46// space for the struct/union return pointer, and space reserved for the
47// first 6 arguments which the caller may use but doesn't have to.
48uint64_t
49getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
50{
51#if FULL_SYSTEM
52    const int NumArgumentRegs = 6;
53    if (number < NumArgumentRegs) {
54        return tc->readIntReg(8 + number);
55    } else {
56        Addr sp = tc->readIntReg(StackPointerReg);
57        FSTranslatingPortProxy* vp = tc->getVirtProxy();
58        uint64_t arg = vp->read<uint64_t>(sp + 92 +
59                            (number-NumArgumentRegs) * sizeof(uint64_t));
60        return arg;
61    }
62#else
63    panic("getArgument() only implemented for FULL_SYSTEM\n");
64    M5_DUMMY_RETURN
65#endif
66}
67
68void
69copyMiscRegs(ThreadContext *src, ThreadContext *dest)
70{
71
72    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
73
74    // Read all the trap level dependent registers and save them off
75    for (int i = 1; i <= MaxTL; i++) {
76        src->setMiscRegNoEffect(MISCREG_TL, i);
77        dest->setMiscRegNoEffect(MISCREG_TL, i);
78
79        dest->setMiscRegNoEffect(MISCREG_TT,
80                src->readMiscRegNoEffect(MISCREG_TT));
81        dest->setMiscRegNoEffect(MISCREG_TPC,
82                src->readMiscRegNoEffect(MISCREG_TPC));
83        dest->setMiscRegNoEffect(MISCREG_TNPC,
84                src->readMiscRegNoEffect(MISCREG_TNPC));
85        dest->setMiscRegNoEffect(MISCREG_TSTATE,
86                src->readMiscRegNoEffect(MISCREG_TSTATE));
87    }
88
89    // Save off the traplevel
90    dest->setMiscRegNoEffect(MISCREG_TL, tl);
91    src->setMiscRegNoEffect(MISCREG_TL, tl);
92
93
94    // ASRs
95//    dest->setMiscRegNoEffect(MISCREG_Y,
96//            src->readMiscRegNoEffect(MISCREG_Y));
97//    dest->setMiscRegNoEffect(MISCREG_CCR,
98//            src->readMiscRegNoEffect(MISCREG_CCR));
99    dest->setMiscRegNoEffect(MISCREG_ASI,
100            src->readMiscRegNoEffect(MISCREG_ASI));
101    dest->setMiscRegNoEffect(MISCREG_TICK,
102            src->readMiscRegNoEffect(MISCREG_TICK));
103    dest->setMiscRegNoEffect(MISCREG_FPRS,
104            src->readMiscRegNoEffect(MISCREG_FPRS));
105    dest->setMiscRegNoEffect(MISCREG_SOFTINT,
106            src->readMiscRegNoEffect(MISCREG_SOFTINT));
107    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
108            src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
109    dest->setMiscRegNoEffect(MISCREG_STICK,
110            src->readMiscRegNoEffect(MISCREG_STICK));
111    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
112            src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
113
114    // Priv Registers
115    dest->setMiscRegNoEffect(MISCREG_TICK,
116            src->readMiscRegNoEffect(MISCREG_TICK));
117    dest->setMiscRegNoEffect(MISCREG_TBA,
118            src->readMiscRegNoEffect(MISCREG_TBA));
119    dest->setMiscRegNoEffect(MISCREG_PSTATE,
120            src->readMiscRegNoEffect(MISCREG_PSTATE));
121    dest->setMiscRegNoEffect(MISCREG_PIL,
122            src->readMiscRegNoEffect(MISCREG_PIL));
123    dest->setMiscReg(MISCREG_CWP,
124            src->readMiscRegNoEffect(MISCREG_CWP));
125//    dest->setMiscRegNoEffect(MISCREG_CANSAVE,
126//            src->readMiscRegNoEffect(MISCREG_CANSAVE));
127//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
128//            src->readMiscRegNoEffect(MISCREG_CANRESTORE));
129//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
130//            src->readMiscRegNoEffect(MISCREG_OTHERWIN));
131//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
132//            src->readMiscRegNoEffect(MISCREG_CLEANWIN));
133//    dest->setMiscRegNoEffect(MISCREG_WSTATE,
134//            src->readMiscRegNoEffect(MISCREG_WSTATE));
135    dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
136
137    // Hyperprivilged registers
138    dest->setMiscRegNoEffect(MISCREG_HPSTATE,
139            src->readMiscRegNoEffect(MISCREG_HPSTATE));
140    dest->setMiscRegNoEffect(MISCREG_HINTP,
141            src->readMiscRegNoEffect(MISCREG_HINTP));
142    dest->setMiscRegNoEffect(MISCREG_HTBA,
143            src->readMiscRegNoEffect(MISCREG_HTBA));
144    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
145            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
146    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
147            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
148
149    // FSR
150    dest->setMiscRegNoEffect(MISCREG_FSR,
151            src->readMiscRegNoEffect(MISCREG_FSR));
152
153    // Strand Status Register
154    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
155            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
156
157    // MMU Registers
158    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
159            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
160    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
161            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
162    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
163            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
164    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
165            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
166
167    // Scratchpad Registers
168    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
169            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
170    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
171            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
172    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
173            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
174    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
175            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
176    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
177            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
178    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
179            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
180    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
181            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
182    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
183            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
184
185    // Queue Registers
186    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
187            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
188    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
189            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
190    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
191            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
192    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
193            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
194    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
195            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
196    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
197            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
198    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
199            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
200    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
201            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
202}
203
204void
205copyRegs(ThreadContext *src, ThreadContext *dest)
206{
207    // First loop through the integer registers.
208    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
209    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
210    // Globals
211    for (int x = 0; x < MaxGL; ++x) {
212        src->setMiscReg(MISCREG_GL, x);
213        dest->setMiscReg(MISCREG_GL, x);
214        // Skip %g0 which is always zero.
215        for (int y = 1; y < 8; y++)
216            dest->setIntReg(y, src->readIntReg(y));
217    }
218    // Locals and ins. Outs are all also ins.
219    for (int x = 0; x < NWindows; ++x) {
220         src->setMiscReg(MISCREG_CWP, x);
221         dest->setMiscReg(MISCREG_CWP, x);
222         for (int y = 16; y < 32; y++)
223             dest->setIntReg(y, src->readIntReg(y));
224    }
225    // Microcode reg and pseudo int regs (misc regs in the integer regfile).
226    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
227        dest->setIntReg(y, src->readIntReg(y));
228
229    // Restore src's GL, CWP
230    src->setMiscReg(MISCREG_GL, old_gl);
231    src->setMiscReg(MISCREG_CWP, old_cwp);
232
233
234    // Then loop through the floating point registers.
235    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
236        dest->setFloatRegBits(i, src->readFloatRegBits(i));
237    }
238
239    // Copy misc. registers
240    copyMiscRegs(src, dest);
241
242    // Lastly copy PC/NPC
243    dest->pcState(src->pcState());
244}
245
246void
247skipFunction(ThreadContext *tc)
248{
249    TheISA::PCState newPC = tc->pcState();
250    newPC.set(tc->readIntReg(ReturnAddressReg));
251    tc->pcState(newPC);
252}
253
254
255void
256initCPU(ThreadContext *tc, int cpuId)
257{
258    static Fault por = new PowerOnReset();
259    if (cpuId == 0)
260        por->invoke(tc);
261}
262
263} // namespace SPARC_ISA
264