utility.cc revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 */
31
32#include "arch/sparc/faults.hh"
33#include "arch/sparc/utility.hh"
34#if FULL_SYSTEM
35#include "arch/sparc/vtophys.hh"
36#include "mem/vport.hh"
37#endif
38
39namespace SparcISA {
40
41
42//The caller uses %o0-%05 for the first 6 arguments even if their floating
43//point. Double precision floating point values take two registers/args.
44//Quads, structs, and unions are passed as pointers. All arguments beyond
45//the sixth are passed on the stack past the 16 word window save area,
46//space for the struct/union return pointer, and space reserved for the
47//first 6 arguments which the caller may use but doesn't have to.
48uint64_t
49getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
50{
51#if FULL_SYSTEM
52    const int NumArgumentRegs = 6;
53    if (number < NumArgumentRegs) {
54        return tc->readIntReg(8 + number);
55    } else {
56        Addr sp = tc->readIntReg(StackPointerReg);
57        VirtualPort *vp = tc->getVirtPort();
58        uint64_t arg = vp->read<uint64_t>(sp + 92 +
59                            (number-NumArgumentRegs) * sizeof(uint64_t));
60        return arg;
61    }
62#else
63    panic("getArgument() only implemented for FULL_SYSTEM\n");
64    M5_DUMMY_RETURN
65#endif
66}
67
68void
69copyMiscRegs(ThreadContext *src, ThreadContext *dest)
70{
71
72    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
73
74    // Read all the trap level dependent registers and save them off
75    for(int i = 1; i <= MaxTL; i++)
76    {
77        src->setMiscRegNoEffect(MISCREG_TL, i);
78        dest->setMiscRegNoEffect(MISCREG_TL, i);
79
80        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
81        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
82        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
83        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
84    }
85
86    // Save off the traplevel
87    dest->setMiscRegNoEffect(MISCREG_TL, tl);
88    src->setMiscRegNoEffect(MISCREG_TL, tl);
89
90
91    // ASRs
92//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
93//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
94    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
95    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
96    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
97    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
98    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
99    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
100    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
101
102    // Priv Registers
103    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
104    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
105    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
106    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
107    dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
108//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
109//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
110//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
111//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
112//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
113    dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
114
115    // Hyperprivilged registers
116    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
117    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
118    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
119    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
120            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
121    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
122            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
123
124    // FSR
125    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
126
127    //Strand Status Register
128    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
129            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
130
131    // MMU Registers
132    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
133            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
134    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
135            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
136    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
137            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
138    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
139            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
140
141    // Scratchpad Registers
142    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
143            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
144    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
145            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
146    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
147            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
148    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
149            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
150    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
151            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
152    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
153            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
154    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
155            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
156    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
157            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
158
159    // Queue Registers
160    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
161            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
162    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
163            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
164    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
165            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
166    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
167            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
168    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
169            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
170    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
171            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
172    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
173            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
174    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
175            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
176}
177
178void
179copyRegs(ThreadContext *src, ThreadContext *dest)
180{
181    //First loop through the integer registers.
182    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
183    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
184    //Globals
185    for (int x = 0; x < MaxGL; ++x) {
186        src->setMiscReg(MISCREG_GL, x);
187        dest->setMiscReg(MISCREG_GL, x);
188        // Skip %g0 which is always zero.
189        for (int y = 1; y < 8; y++)
190            dest->setIntReg(y, src->readIntReg(y));
191    }
192    //Locals and ins. Outs are all also ins.
193    for (int x = 0; x < NWindows; ++x) {
194         src->setMiscReg(MISCREG_CWP, x);
195         dest->setMiscReg(MISCREG_CWP, x);
196         for (int y = 16; y < 32; y++)
197             dest->setIntReg(y, src->readIntReg(y));
198    }
199    //Microcode reg and pseudo int regs (misc regs in the integer regfile).
200    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
201        dest->setIntReg(y, src->readIntReg(y));
202
203    //Restore src's GL, CWP
204    src->setMiscReg(MISCREG_GL, old_gl);
205    src->setMiscReg(MISCREG_CWP, old_cwp);
206
207
208    // Then loop through the floating point registers.
209    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
210        dest->setFloatRegBits(i, src->readFloatRegBits(i));
211    }
212
213    // Copy misc. registers
214    copyMiscRegs(src, dest);
215
216    // Lastly copy PC/NPC
217    dest->pcState(src->pcState());
218}
219
220void
221skipFunction(ThreadContext *tc)
222{
223    TheISA::PCState newPC = tc->pcState();
224    newPC.set(tc->readIntReg(ReturnAddressReg));
225    tc->pcState(newPC);
226}
227
228
229void
230initCPU(ThreadContext *tc, int cpuId)
231{
232    static Fault por = new PowerOnReset();
233    if (cpuId == 0)
234        por->invoke(tc);
235}
236
237} //namespace SPARC_ISA
238