utility.cc revision 7678:f19b6a3a8cec
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/faults.hh" 33#include "arch/sparc/utility.hh" 34#if FULL_SYSTEM 35#include "arch/sparc/vtophys.hh" 36#include "mem/vport.hh" 37#endif 38 39namespace SparcISA { 40 41 42//The caller uses %o0-%05 for the first 6 arguments even if their floating 43//point. Double precision floating point values take two registers/args. 44//Quads, structs, and unions are passed as pointers. All arguments beyond 45//the sixth are passed on the stack past the 16 word window save area, 46//space for the struct/union return pointer, and space reserved for the 47//first 6 arguments which the caller may use but doesn't have to. 48uint64_t getArgument(ThreadContext *tc, int number, bool fp) { 49#if FULL_SYSTEM 50 const int NumArgumentRegs = 6; 51 if (number < NumArgumentRegs) { 52 return tc->readIntReg(8 + number); 53 } else { 54 Addr sp = tc->readIntReg(StackPointerReg); 55 VirtualPort *vp = tc->getVirtPort(); 56 uint64_t arg = vp->read<uint64_t>(sp + 92 + 57 (number-NumArgumentRegs) * sizeof(uint64_t)); 58 return arg; 59 } 60#else 61 panic("getArgument() only implemented for FULL_SYSTEM\n"); 62 M5_DUMMY_RETURN 63#endif 64} 65 66void 67copyMiscRegs(ThreadContext *src, ThreadContext *dest) 68{ 69 70 uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 71 72 // Read all the trap level dependent registers and save them off 73 for(int i = 1; i <= MaxTL; i++) 74 { 75 src->setMiscRegNoEffect(MISCREG_TL, i); 76 dest->setMiscRegNoEffect(MISCREG_TL, i); 77 78 dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); 79 dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); 80 dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); 81 dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); 82 } 83 84 // Save off the traplevel 85 dest->setMiscRegNoEffect(MISCREG_TL, tl); 86 src->setMiscRegNoEffect(MISCREG_TL, tl); 87 88 89 // ASRs 90// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); 91// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); 92 dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); 93 dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 94 dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); 95 dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); 96 dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 97 dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); 98 dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 99 100 // Priv Registers 101 dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 102 dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); 103 dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); 104 dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); 105 dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); 106// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); 107// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 108// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 109// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 110// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); 111 dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 112 113 // Hyperprivilged registers 114 dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); 115 dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); 116 dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); 117 dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 118 src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 119 dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 120 src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 121 122 // FSR 123 dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); 124 125 //Strand Status Register 126 dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 127 src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 128 129 // MMU Registers 130 dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 131 src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 132 dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 133 src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 134 dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 135 src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 136 dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 137 src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 138 139 // Scratchpad Registers 140 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 141 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 142 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 143 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 144 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 145 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 146 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 147 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 148 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 149 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 150 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 151 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 152 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 153 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 154 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 155 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 156 157 // Queue Registers 158 dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 159 src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 160 dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 161 src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 162 dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 163 src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 164 dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 165 src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 166 dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 167 src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 168 dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 169 src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 170 dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 171 src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 172 dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 173 src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 174} 175 176void 177copyRegs(ThreadContext *src, ThreadContext *dest) 178{ 179 //First loop through the integer registers. 180 int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 181 int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 182 //Globals 183 for (int x = 0; x < MaxGL; ++x) { 184 src->setMiscReg(MISCREG_GL, x); 185 dest->setMiscReg(MISCREG_GL, x); 186 // Skip %g0 which is always zero. 187 for (int y = 1; y < 8; y++) 188 dest->setIntReg(y, src->readIntReg(y)); 189 } 190 //Locals and ins. Outs are all also ins. 191 for (int x = 0; x < NWindows; ++x) { 192 src->setMiscReg(MISCREG_CWP, x); 193 dest->setMiscReg(MISCREG_CWP, x); 194 for (int y = 16; y < 32; y++) 195 dest->setIntReg(y, src->readIntReg(y)); 196 } 197 //Microcode reg and pseudo int regs (misc regs in the integer regfile). 198 for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 199 dest->setIntReg(y, src->readIntReg(y)); 200 201 //Restore src's GL, CWP 202 src->setMiscReg(MISCREG_GL, old_gl); 203 src->setMiscReg(MISCREG_CWP, old_cwp); 204 205 206 // Then loop through the floating point registers. 207 for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 208 dest->setFloatRegBits(i, src->readFloatRegBits(i)); 209 } 210 211 // Copy misc. registers 212 copyMiscRegs(src, dest); 213 214 215 // Lastly copy PC/NPC 216 dest->setPC(src->readPC()); 217 dest->setNextPC(src->readNextPC()); 218 dest->setNextNPC(src->readNextNPC()); 219} 220 221void 222initCPU(ThreadContext *tc, int cpuId) 223{ 224 static Fault por = new PowerOnReset(); 225 if (cpuId == 0) 226 por->invoke(tc); 227} 228 229} //namespace SPARC_ISA 230