utility.cc revision 13611:c8b7847b4171
110259SAndrew.Bardsley@arm.com/*
210259SAndrew.Bardsley@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
310259SAndrew.Bardsley@arm.com * All rights reserved.
410259SAndrew.Bardsley@arm.com *
510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without
610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are
710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright
810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer;
910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright
1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the
1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution;
1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its
1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from
1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission.
1510259SAndrew.Bardsley@arm.com *
1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710259SAndrew.Bardsley@arm.com *
2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black
2910259SAndrew.Bardsley@arm.com *          Ali Saidi
3010259SAndrew.Bardsley@arm.com */
3110259SAndrew.Bardsley@arm.com
3210259SAndrew.Bardsley@arm.com#include "arch/sparc/utility.hh"
3310259SAndrew.Bardsley@arm.com
3410259SAndrew.Bardsley@arm.com#include "arch/sparc/faults.hh"
3510259SAndrew.Bardsley@arm.com#include "arch/sparc/vtophys.hh"
3610259SAndrew.Bardsley@arm.com#include "mem/fs_translating_port_proxy.hh"
3710259SAndrew.Bardsley@arm.com
3810259SAndrew.Bardsley@arm.comnamespace SparcISA {
3910259SAndrew.Bardsley@arm.com
4010259SAndrew.Bardsley@arm.com
4110259SAndrew.Bardsley@arm.com// The caller uses %o0-%05 for the first 6 arguments even if their floating
4210259SAndrew.Bardsley@arm.com// point. Double precision floating point values take two registers/args.
4310259SAndrew.Bardsley@arm.com// Quads, structs, and unions are passed as pointers. All arguments beyond
4410259SAndrew.Bardsley@arm.com// the sixth are passed on the stack past the 16 word window save area,
4510259SAndrew.Bardsley@arm.com// space for the struct/union return pointer, and space reserved for the
4610259SAndrew.Bardsley@arm.com// first 6 arguments which the caller may use but doesn't have to.
4710259SAndrew.Bardsley@arm.comuint64_t
4810259SAndrew.Bardsley@arm.comgetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
4910259SAndrew.Bardsley@arm.com{
5010259SAndrew.Bardsley@arm.com    if (!FullSystem) {
5110259SAndrew.Bardsley@arm.com        panic("getArgument() only implemented for full system\n");
5210259SAndrew.Bardsley@arm.com        M5_DUMMY_RETURN
5312334Sgabeblack@google.com    }
5412334Sgabeblack@google.com
5510259SAndrew.Bardsley@arm.com    const int NumArgumentRegs = 6;
5610259SAndrew.Bardsley@arm.com    if (number < NumArgumentRegs) {
5710259SAndrew.Bardsley@arm.com        return tc->readIntReg(8 + number);
5810259SAndrew.Bardsley@arm.com    } else {
5910259SAndrew.Bardsley@arm.com        Addr sp = tc->readIntReg(StackPointerReg);
6010259SAndrew.Bardsley@arm.com        FSTranslatingPortProxy &vp = tc->getVirtProxy();
6110259SAndrew.Bardsley@arm.com        uint64_t arg = vp.read<uint64_t>(sp + 92 +
6210259SAndrew.Bardsley@arm.com                            (number-NumArgumentRegs) * sizeof(uint64_t));
6310259SAndrew.Bardsley@arm.com        return arg;
6410259SAndrew.Bardsley@arm.com    }
6510259SAndrew.Bardsley@arm.com}
6610259SAndrew.Bardsley@arm.com
6710259SAndrew.Bardsley@arm.comvoid
6810259SAndrew.Bardsley@arm.comcopyMiscRegs(ThreadContext *src, ThreadContext *dest)
6910259SAndrew.Bardsley@arm.com{
7010259SAndrew.Bardsley@arm.com
7110259SAndrew.Bardsley@arm.com    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
7210259SAndrew.Bardsley@arm.com
7310259SAndrew.Bardsley@arm.com    // Read all the trap level dependent registers and save them off
7410259SAndrew.Bardsley@arm.com    for (int i = 1; i <= MaxTL; i++) {
7510259SAndrew.Bardsley@arm.com        src->setMiscRegNoEffect(MISCREG_TL, i);
7610259SAndrew.Bardsley@arm.com        dest->setMiscRegNoEffect(MISCREG_TL, i);
7710259SAndrew.Bardsley@arm.com
7810259SAndrew.Bardsley@arm.com        dest->setMiscRegNoEffect(MISCREG_TT,
7910259SAndrew.Bardsley@arm.com                src->readMiscRegNoEffect(MISCREG_TT));
8010259SAndrew.Bardsley@arm.com        dest->setMiscRegNoEffect(MISCREG_TPC,
8110259SAndrew.Bardsley@arm.com                src->readMiscRegNoEffect(MISCREG_TPC));
8210259SAndrew.Bardsley@arm.com        dest->setMiscRegNoEffect(MISCREG_TNPC,
8310259SAndrew.Bardsley@arm.com                src->readMiscRegNoEffect(MISCREG_TNPC));
8410259SAndrew.Bardsley@arm.com        dest->setMiscRegNoEffect(MISCREG_TSTATE,
8510259SAndrew.Bardsley@arm.com                src->readMiscRegNoEffect(MISCREG_TSTATE));
8610259SAndrew.Bardsley@arm.com    }
8710259SAndrew.Bardsley@arm.com
8810259SAndrew.Bardsley@arm.com    // Save off the traplevel
8910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_TL, tl);
9010259SAndrew.Bardsley@arm.com    src->setMiscRegNoEffect(MISCREG_TL, tl);
9110259SAndrew.Bardsley@arm.com
9210259SAndrew.Bardsley@arm.com
9310259SAndrew.Bardsley@arm.com    // ASRs
9410259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_Y,
9510259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_Y));
9610259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_CCR,
9710259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_CCR));
9810259SAndrew.Bardsley@arm.com    dest->setMiscReg(MISCREG_ASI,
9910259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_ASI));
10010259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_TICK,
10110259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_TICK));
10210259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_FPRS,
10310259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_FPRS));
10410259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SOFTINT,
10510259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SOFTINT));
10610259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR,
10710259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
10810259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_STICK,
10910259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_STICK));
11010259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR,
11110259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
11210259SAndrew.Bardsley@arm.com
11310259SAndrew.Bardsley@arm.com    // Priv Registers
11410259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_TICK,
11510259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_TICK));
11610259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_TBA,
11710259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_TBA));
11810259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_PSTATE,
11910259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_PSTATE));
12010259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_PIL,
12113449Sgabeblack@google.com            src->readMiscRegNoEffect(MISCREG_PIL));
12213449Sgabeblack@google.com    dest->setMiscReg(MISCREG_CWP,
12313449Sgabeblack@google.com            src->readMiscRegNoEffect(MISCREG_CWP));
12413449Sgabeblack@google.com//    dest->setMiscRegNoEffect(MISCREG_CANSAVE,
12513449Sgabeblack@google.com//            src->readMiscRegNoEffect(MISCREG_CANSAVE));
12610259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE,
12710259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_CANRESTORE));
12810259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN,
12910259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_OTHERWIN));
13010259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN,
13110259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_CLEANWIN));
13210259SAndrew.Bardsley@arm.com//    dest->setMiscRegNoEffect(MISCREG_WSTATE,
13310259SAndrew.Bardsley@arm.com//            src->readMiscRegNoEffect(MISCREG_WSTATE));
13410259SAndrew.Bardsley@arm.com    dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
13510259SAndrew.Bardsley@arm.com
13610259SAndrew.Bardsley@arm.com    // Hyperprivilged registers
13710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_HPSTATE,
13810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_HPSTATE));
13910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_HINTP,
14010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_HINTP));
14110259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_HTBA,
14210259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_HTBA));
14310259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
14410259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
14510259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
14610259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
14710259SAndrew.Bardsley@arm.com
14810259SAndrew.Bardsley@arm.com    // FSR
14910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_FSR,
15010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_FSR));
15110259SAndrew.Bardsley@arm.com
15210259SAndrew.Bardsley@arm.com    // Strand Status Register
15310259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
15410259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
15510259SAndrew.Bardsley@arm.com
15610259SAndrew.Bardsley@arm.com    // MMU Registers
15710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
15810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
15910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
16010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
16110259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
16210259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
16310259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
16410259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
16510259SAndrew.Bardsley@arm.com
16610259SAndrew.Bardsley@arm.com    // Scratchpad Registers
16710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
16810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
16910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
17010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
17110259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
17210259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
17310259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
17410259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
17510259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
17610259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
17710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
17810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
17910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
18010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
18110259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
18210259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
18310259SAndrew.Bardsley@arm.com
18410259SAndrew.Bardsley@arm.com    // Queue Registers
18510259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
18610259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
18710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
18810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
18910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
19010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
19110259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
19210259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
19310259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
19410259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
19510259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
19610259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
19710259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
19810259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
19910259SAndrew.Bardsley@arm.com    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
20010259SAndrew.Bardsley@arm.com            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
20110259SAndrew.Bardsley@arm.com}
20210259SAndrew.Bardsley@arm.com
20310259SAndrew.Bardsley@arm.comvoid
20410259SAndrew.Bardsley@arm.comcopyRegs(ThreadContext *src, ThreadContext *dest)
20510259SAndrew.Bardsley@arm.com{
20610259SAndrew.Bardsley@arm.com    // First loop through the integer registers.
20710259SAndrew.Bardsley@arm.com    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
20810259SAndrew.Bardsley@arm.com    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
20910259SAndrew.Bardsley@arm.com    // Globals
21010259SAndrew.Bardsley@arm.com    for (int x = 0; x < MaxGL; ++x) {
21110259SAndrew.Bardsley@arm.com        src->setMiscReg(MISCREG_GL, x);
21210259SAndrew.Bardsley@arm.com        dest->setMiscReg(MISCREG_GL, x);
21310259SAndrew.Bardsley@arm.com        // Skip %g0 which is always zero.
21410259SAndrew.Bardsley@arm.com        for (int y = 1; y < 8; y++)
21510259SAndrew.Bardsley@arm.com            dest->setIntReg(y, src->readIntReg(y));
21610259SAndrew.Bardsley@arm.com    }
21710259SAndrew.Bardsley@arm.com    // Locals and ins. Outs are all also ins.
21810259SAndrew.Bardsley@arm.com    for (int x = 0; x < NWindows; ++x) {
21910259SAndrew.Bardsley@arm.com         src->setMiscReg(MISCREG_CWP, x);
22010259SAndrew.Bardsley@arm.com         dest->setMiscReg(MISCREG_CWP, x);
22110259SAndrew.Bardsley@arm.com         for (int y = 16; y < 32; y++)
22210259SAndrew.Bardsley@arm.com             dest->setIntReg(y, src->readIntReg(y));
22310259SAndrew.Bardsley@arm.com    }
22410259SAndrew.Bardsley@arm.com    // Microcode reg and pseudo int regs (misc regs in the integer regfile).
22510259SAndrew.Bardsley@arm.com    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
22610259SAndrew.Bardsley@arm.com        dest->setIntReg(y, src->readIntReg(y));
22710259SAndrew.Bardsley@arm.com
22810259SAndrew.Bardsley@arm.com    // Restore src's GL, CWP
22910259SAndrew.Bardsley@arm.com    src->setMiscReg(MISCREG_GL, old_gl);
23010259SAndrew.Bardsley@arm.com    src->setMiscReg(MISCREG_CWP, old_cwp);
23110259SAndrew.Bardsley@arm.com
23210259SAndrew.Bardsley@arm.com
23310259SAndrew.Bardsley@arm.com    // Then loop through the floating point registers.
23410259SAndrew.Bardsley@arm.com    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
23510259SAndrew.Bardsley@arm.com        dest->setFloatReg(i, src->readFloatReg(i));
23610259SAndrew.Bardsley@arm.com    }
23710259SAndrew.Bardsley@arm.com
23810259SAndrew.Bardsley@arm.com    // Would need to add condition-code regs if implemented
23910259SAndrew.Bardsley@arm.com    assert(NumCCRegs == 0);
24010259SAndrew.Bardsley@arm.com
24110259SAndrew.Bardsley@arm.com    // Copy misc. registers
24210259SAndrew.Bardsley@arm.com    copyMiscRegs(src, dest);
24310259SAndrew.Bardsley@arm.com
24410259SAndrew.Bardsley@arm.com    // Lastly copy PC/NPC
24510259SAndrew.Bardsley@arm.com    dest->pcState(src->pcState());
24610259SAndrew.Bardsley@arm.com}
24710259SAndrew.Bardsley@arm.com
24810259SAndrew.Bardsley@arm.comvoid
24910259SAndrew.Bardsley@arm.comskipFunction(ThreadContext *tc)
25010259SAndrew.Bardsley@arm.com{
25110259SAndrew.Bardsley@arm.com    TheISA::PCState newPC = tc->pcState();
25210259SAndrew.Bardsley@arm.com    newPC.set(tc->readIntReg(ReturnAddressReg));
25310259SAndrew.Bardsley@arm.com    tc->pcState(newPC);
25410259SAndrew.Bardsley@arm.com}
25510259SAndrew.Bardsley@arm.com
25610259SAndrew.Bardsley@arm.com
25710259SAndrew.Bardsley@arm.comvoid
25810259SAndrew.Bardsley@arm.cominitCPU(ThreadContext *tc, int cpuId)
25910259SAndrew.Bardsley@arm.com{
26010259SAndrew.Bardsley@arm.com    static Fault por = std::make_shared<PowerOnReset>();
26110259SAndrew.Bardsley@arm.com    if (cpuId == 0)
26210259SAndrew.Bardsley@arm.com        por->invoke(tc);
26310259SAndrew.Bardsley@arm.com}
26410259SAndrew.Bardsley@arm.com
26510259SAndrew.Bardsley@arm.com} // namespace SPARC_ISA
26610259SAndrew.Bardsley@arm.com